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XRT75L06D Datasheet(PDF) 6 Page - Exar Corporation

Part No. XRT75L06D
Description  SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT75L06D Datasheet(HTML) 6 Page - Exar Corporation

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SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
III
60
FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 61
FIGURE 42. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME .......................................................................................... 62
FIGURE 43. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE....................................................................................... 63
FIGURE 44. AN ILLUSTRATION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE... 64
FIGURE 45. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE'S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO
AN
STS-1 SPE ............................................................................................................................................................. 64
7.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ........................................... 65
FIGURE 46. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .............................. 66
FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3
SIGNAL THAT HAS A BIT RATE OF
44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL ............................................................... 67
FIGURE 48. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL
THAT HAS A BIT RATE OF
44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL ........................................................................... 69
7.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS.................................................................................. 69
7.3.1 THE CONCEPT OF AN STS-1 SPE POINTER............................................................................................................. 69
FIGURE 49. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES .................................... 70
FIGURE 50. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION
OF THE
J1 BYTE, DESIGNATED ........................................................................................................................................ 71
FIGURE 51. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2
BYTES
) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ............................... 71
7.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK .................................................................................... 71
7.3.3 CAUSES OF POINTER ADJUSTMENTS ..................................................................................................................... 72
FIGURE 52. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER ............................................................. 73
FIGURE 53. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS
DESIGNATED
.................................................................................................................................................................. 74
FIGURE 54. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS
DESIGNATED
.................................................................................................................................................................. 75
7.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ................................................................................. 76
7.4 CLOCK GAPPING JITTER ................................................................................................................................ 76
FIGURE 55. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION.................................. 76
7.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR
DS3 APPLICATIONS ...................................................................................................................................... 77
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3 APPLICATIONS .. 77
7.5.1 DS3 DE-MAPPING JITTER........................................................................................................................................... 78
7.5.2 SINGLE POINTER ADJUSTMENT ............................................................................................................................... 78
FIGURE 56. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO ......................................................................................... 78
7.5.3 POINTER BURST.......................................................................................................................................................... 78
FIGURE 57. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO ..................................................................................... 79
7.5.4 PHASE TRANSIENTS................................................................................................................................................... 79
FIGURE 58. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO ..................................................................... 79
7.5.5 87-3 PATTERN.............................................................................................................................................................. 80
FIGURE 59. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN ............................................................. 80
7.5.6 87-3 ADD ....................................................................................................................................................................... 80
FIGURE 60. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN ................................................................................ 81
7.5.7 87-3 CANCEL................................................................................................................................................................ 81
FIGURE 61. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO................................................................................ 81
7.5.8 CONTINUOUS PATTERN ............................................................................................................................................. 82
FIGURE 62. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO ................................................................ 82
7.5.9 CONTINUOUS ADD ..................................................................................................................................................... 82
FIGURE 63. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO......................................................................... 83
7.5.10 CONTINUOUS CANCEL ............................................................................................................................................. 83
FIGURE 64. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO ................................................................... 83
7.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997...................................... 84
7.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM
APPLICATION................................................................................................................................................. 84
7.7.1 INTRINSIC JITTER TEST RESULTS............................................................................................................................ 84
TABLE 20: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ..................................... 84
7.7.2 WANDER MEASUREMENT TEST RESULTS.............................................................................................................. 85
7.8 DESIGNING WITH THE LIU .............................................................................................................................. 85
7.8.1 HOW TO DESIGN AND CONFIGURE THE LIU TO PERMIT A SYSTEM TO MEET THE ABOVE-MENTIONED INTRINSIC
JITTER AND WANDER REQUIREMENTS.................................................................................................................... 85
FIGURE 65. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS .......................... 85
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 .................................................... 86
CHANNEL 1 ADDRESS LOCATION = 0X0E ............................................ 86
CHANNEL 2 ADDRESS LOCATION = 0X16 ............................................ 86


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