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XRT75L06D Datasheet(PDF) 5 Page - Exar Corporation

Part No. XRT75L06D
Description  SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT75L06D Datasheet(HTML) 5 Page - Exar Corporation

 
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XRT75L06D
REV. 1.0.4
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
II
3.4 TRANSMIT PULSE SHAPER ............................................................................................................................ 27
FIGURE 20. TRANSMIT PULSE SHAPE TEST CIRCUIT ....................................................................................................................... 27
3.4.1 GUIDELINES FOR USING TRANSMIT BUILD OUT CIRCUIT .................................................................................... 27
3.5 E3 LINE SIDE PARAMETERS .......................................................................................................................... 28
FIGURE 21. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703....................................................................... 28
TABLE 3: E3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS ....................................................... 29
FIGURE 22. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS .......................... 30
TABLE 4: STS-1 PULSE MASK EQUATIONS ..................................................................................................................................... 30
TABLE 5: STS-1 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-253) .............................. 31
FIGURE 23. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499 ................................................................... 31
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................................................ 32
TABLE 7: DS3 TRANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS (GR-499) ................................. 32
3.6 TRANSMIT DRIVE MONITOR ........................................................................................................................... 33
FIGURE 24. TRANSMIT DRIVER MONITOR SET-UP. ........................................................................................................................... 33
3.7 TRANSMITTER SECTION ON/OFF .................................................................................................................. 33
4.0 JITTER ................................................................................................................................................... 34
4.1 JITTER TOLERANCE........................................................................................................................................ 34
FIGURE 25. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 34
4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS .................................................................................................. 34
FIGURE 26. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 35
4.1.2 E3 JITTER TOLERANCE REQUIREMENTS................................................................................................................ 35
FIGURE 27. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 35
TABLE 8: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................... 36
4.2 JITTER TRANSFER........................................................................................................................................... 36
TABLE 9: JITTER TRANSFER SPECIFICATION/REFERENCES .............................................................................................................. 36
4.3 JITTER ATTENUATOR ..................................................................................................................................... 36
TABLE 10: JITTER TRANSFER PASS MASKS .................................................................................................................................... 37
FIGURE 28. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 37
4.3.1 JITTER GENERATION.................................................................................................................................................. 37
5.0 DIAGNOSTIC FEATURES..................................................................................................................... 38
5.1 PRBS GENERATOR AND DETECTOR ............................................................................................................ 38
FIGURE 29. PRBS MODE ............................................................................................................................................................. 38
5.2 LOOPBACKS .................................................................................................................................................... 39
5.2.1 ANALOG LOOPBACK.................................................................................................................................................. 39
FIGURE 30. ANALOG LOOPBACK..................................................................................................................................................... 39
5.2.2 DIGITAL LOOPBACK ................................................................................................................................................... 40
FIGURE 31. DIGITAL LOOPBACK...................................................................................................................................................... 40
5.2.3 REMOTE LOOPBACK .................................................................................................................................................. 40
FIGURE 32. REMOTE LOOPBACK .................................................................................................................................................... 40
5.3 TRANSMIT ALL ONES (TAOS) ........................................................................................................................ 41
FIGURE 33. TRANSMIT ALL ONES (TAOS)...................................................................................................................................... 41
6.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 42
TABLE 11: SELECTING THE MICROPROCESSOR INTERFACE MODE ................................................................................................... 42
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK.................................................................. 42
6.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ............................................................................ 43
TABLE 12: XRT75L06D MICROPROCESSOR INTERFACE SIGNALS ................................................................................................... 43
6.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION............................................................................. 44
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ........................... 45
TABLE 13: ASYNCHRONOUS TIMING SPECIFICATIONS ...................................................................................................................... 45
FIGURE 36. SYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ............................. 46
TABLE 14: SYNCHRONOUS TIMING SPECIFICATIONS ........................................................................................................................ 46
FIGURE 37. INTERRUPT PROCESS................................................................................................................................................... 47
6.2.1 HARDWARE RESET: ................................................................................................................................................... 48
TABLE 15: REGISTER MAP AND BIT NAMES .................................................................................................................................... 48
TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ......................................................................................................................... 49
TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL N REGISTERS (N = 0,1,2,3,4,5) ................................................................... 49
TABLE 18: REGISTER MAP DESCRIPTION - CHANNEL N ................................................................................................................... 51
7.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ................................................................. 56
7.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .............................. 56
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ........ 57
7.2 MAPPING/DE-MAPPING JITTER/WANDER .................................................................................................... 58
7.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................... 58
FIGURE 39. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME .............................................................................................. 59
FIGURE 40. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED


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