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XRT75L04DIV Datasheet(PDF) 10 Page - Exar Corporation |
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XRT75L04DIV Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 98 page  XRT75L04D áç áç áç áç FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1 6 88 TxClkINV/ SClk I Hardware Mode: Transmit Clock Invert Host Mode: Serial Clock Input: Function of this pin depends on whether the XRT75L04D is configured to oper- ate in Hardware mode or Host mode. In Hardware mode, setting this input pin “High” configures all three Transmitters to sample the TPOS_n and TNEG_n data on the rising edge of the TxCLK_n . NOTES: 1. If the XRT75L04D is configured in HOST mode, this pin functions as SClk input pin (please refer to the pin description for Microprocessor interface). 152 TxMON I Transmitter Monitor: When this pin is pulled “High”, MTIP and MRING are connected internally to TTIP and TRING and allows self monitoring of the transmitter. 51 48 170 173 TAOS_0 TAOS_1 TAOS_2 TAOS_3 I Transmit All Ones Select - Channel 0: Transmit All Ones Select - Channel 1: Transmit All Ones Select - Channel 2: Transmit All Ones Select - Channel 3: A “High" on this pin causes the Transmitter Section of Channel_n to generate and transmit a continuous AMI all “1’s” pattern onto the line. The frequency of this “1’s” pattern is determined by TxClk_n. NOTES: 1. This input pin is ignored if the XRT75L04D is operating in the HOST Mode and should be tied to GND. 2. Analog Loopback and Remote Loopback have priority over request. 3. This pin is internally pulled down. TRANSMIT INTERFACE PIN #SIGNAL NAME TYPE DESCRIPTION |
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