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XRT72L54 Datasheet(PDF) 6 Page - Exar Corporation |
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XRT72L54 Datasheet(HTML) 6 Page - Exar Corporation |
6 / 484 page XRT72L54 áç áç áç áç FOUR CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER REV. P1.1.2 PRELIMINARY IV TXE3 TTB-6 REGISTER (ADDRESS = 0X3E) ........................................................................................... 111 TXE3 TTB-7 REGISTER (ADDRESS = 0X3F) ........................................................................................... 111 TXE3 TTB-8 REGISTER (ADDRESS = 0X40) ........................................................................................... 112 TXE3 TTB-9 REGISTER (ADDRESS = 0X41) ........................................................................................... 112 TXE3 TTB-10 REGISTER (ADDRESS = 0X42) ......................................................................................... 113 TXE3 TTB-11 REGISTER (ADDRESS = 0X43) ......................................................................................... 113 TXE3 TTB-12 REGISTER (ADDRESS = 0X44) ......................................................................................... 113 TXE3 TTB-13 REGISTER (ADDRESS = 0X45) ......................................................................................... 114 TXE3 TTB-14 REGISTER (ADDRESS = 0X46) ......................................................................................... 114 TXE3 TTB-15 REGISTER (ADDRESS = 0X47) ......................................................................................... 114 TXE3 FA1 ERROR MASK REGISTER (ADDRESS = 0X48) ......................................................................... 115 TXE3 FA2 ERROR MASK REGISTER (ADDRESS = 0X49) ......................................................................... 115 TXE3 BIP-8 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 115 2.4.7 Transmit E3 Framer Configuration Registers (ITU-T G.751) ................................................................. 116 TXE3 CONFIGURATION REGISTER (ADDRESS = 0X30) ............................................................................ 116 TXE3 LAPD CONFIGURATION REGISTER (ADDRESS = 0X33) .................................................................. 117 TXE3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) ...................................................... 118 TXE3 SERVICE BITS REGISTER (ADDRESS = 0X35) ................................................................................ 119 TXE3 FAS ERROR MASK REGISTER - 0 (ADDRESS = 0X48) ................................................................... 119 TXE3 FAS ERROR MASK REGISTER - 1 (ADDRESS = 0X49) ................................................................... 119 TXE3 BIP-4 ERROR MASK REGISTER (ADDRESS = 0X4A) ...................................................................... 120 2.4.8 Performance Monitor Registers ............................................................................................................. 120 PMON LCV EVENT COUNT REGISTER - LSB (ADDRESS = 0X51) ........................................................... 120 PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - MSB (ADDRESS = 0X52) ................................... 121 PMON FRAMING BIT/BYTE ERROR COUNT REGISTER - LSB (ADDRESS = 0X53) .................................... 121 PMON PARITY ERROR COUNT REGISTER - MSB (ADDRESS = 0X54) ..................................................... 121 PMON PARITY ERROR COUNT REGISTER - LSB (ADDRESS = 0X55) ...................................................... 121 PMON FEBE EVENT COUNT REGISTER - MSB (ADDRESS = 0X56) ........................................................ 122 PMON FEBE EVENT COUNT REGISTER - LSB (ADDRESS = 0X57) ......................................................... 122 PMON CP-BIT ERROR COUNT REGISTER - MSB (ADDRESS = 0X58) ..................................................... 122 PMON CP-BIT ERROR COUNT REGISTER - LSB (ADDRESS = 0X59) ...................................................... 123 PMON HOLDING REGISTER (ADDRESS = 0X6C) ..................................................................................... 123 ONE-SECOND ERROR STATUS REGISTER (ADDRESS = 0X6D) ................................................................ 123 LCV - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X6E) ............................................ 124 LCV - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X6F) .............................................. 124 FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X70) ................ 124 FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X71) ................. 125 FRAME CP-BIT ERRORS - ONE-SECOND ACCUMULATOR REGISTER - MSB (ADDRESS = 0X72) ............... 125 FRAME PARITY ERRORS - ONE-SECOND ACCUMULATOR REGISTER - LSB (ADDRESS = 0X73) ................. 125 LINE INTERFACE DRIVE REGISTER (ADDRESS = 0X80) ............................................................................ 126 LINE INTERFACE SCAN REGISTER (ADDRESS = 0X81) ............................................................................. 128 HDLC CONTROL REGISTER (ADDRESS = 0X82) ..................................................................................... 129 2.5 THE LOSS OF CLOCK ENABLE FEATURE ............................................................................................................. 129 ADDRESS = 0X01, FRAMER I/O CONTROL REGISTER .............................................................................. 130 2.6 USING THE PMON HOLDING REGISTER .............................................................................................................. 130 2.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER MICROPROCESSOR INTERFACE SECTION ................................. 130 TABLE 6: LIST OF ALL OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS WITHIN EACH CHANNEL OF THE XRT72L54 FRAMER DEVICE ...................................................................................................... 131 TABLE 7: A LISTING OF THE XRT72L54 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR DS3 APPLICA- TIONS ) ................................................................................................................................................... 131 TABLE 8: A LISTING OF THE XRT72L54 FRAMER DEVICE INTERRUPT BLOCK REGISTERS (FOR E3, ITU-T G.832 APPLICATIONS) ...................................................................................................................................... 131 TABLE 9: A LISTING OF THE XRT72L54 FRAMER DEVICE INTERRUPT BLOCK REGISTER (FOR E3, ITU-T G.751 APPLICATIONS) ...................................................................................................................................... 132 BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05) ...................................................................... 132 |
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