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XRT71D03 Datasheet(PDF) 6 Page - Exar Corporation

Part No. XRT71D03
Description  3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
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Maker  EXAR [Exar Corporation]
Homepage  http://www.exar.com
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XRT71D03 Datasheet(HTML) 6 Page - Exar Corporation

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3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR
REV. 1.2.0
5
20
DS3/E3_0
I
DS3/E3 Select Input - channel 0:
See description pin 8.
Internal 50 K Ohm pull-down resistor.
21
DJA_0/SCLK
I
Hardware Mode
Disable Jitter Attenuator Input - Channel 0:
An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will
be passed through without jitter attenuation.
Host Mode
Microprocessor Serial Interface Clock Signal:
This signal will be used to sample the data on the SDI pin, on the rising edge
of this signal. Additionally, during “Read” operations, the Microprocessor Serial
Interface will update the SDO output on the falling edge of this signal.
Internal 50 K Ohm pull-down resistor.
22
GND
****
Digital Ground
23
RPOS_2
I
Received Positive Data (Jittery) Input: - channel 2:
Data that is input on this pin is sampled on either the rising or falling edge of
RCLK depending on the setting of the RCLKES pin (pin 10).
If RCLKES is “high”, then RPOS will be sampled on the falling edge of RCLK.
If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.
Internal 50 K Ohm pull-up resistor.
24
RNEG_2
I
Received Negative Data (Jittery) - channel 2:
The input jittery negative data is sampled either on the rising or falling edge of
RCLK depending on the setting of RCLKES.
If RCLKES is “high”, then RNEG will be sampled on the falling edge of RCLK.
If RCLKES is “low”, then RPOS will be sampled on the rising edge of RCLK.
This pin is typically tied to the “RNEG” output pin of the LIU.
Internal 50 K Ohm pull-up resistor.
25
VDD
****
Digital Power Supply = 5V±5% or 3.3V±5%
26
RCLK_2
I
Received Clock (Jittery) - channel 2:
Clock input RCLK2 should be connected to the recovered clock.
Internal 50 K Ohm pull-up resistor.
27
GND
****
Digital Ground
28
MCLK_2
I
Master Clock Input - channel 2:
Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/-
20ppm. This clock must be continuous and jitter free with duty cycle between
30 to 70%.
It is permissible to use the EXCLK signal orSTS1 clock.
Internal 50 K Ohm pull-up resistor.
29
DJA_2/CS
I
Hardware Mode
Disable Jitter Attenuator Input - Channel 2:
See description of pin 25
Host Mode
Chip Select Input:
An active-low input enables the serial interface.
Internal 50 K Ohm pull-down resistor.
30
STS1_2
I
SONET STS1 Mode Select - channel 2:
See description pin 19
PIN DESCRIPTION
PIN #NAME
TYPE
DESCRIPTION


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