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XRT16C854 Datasheet(PDF) 13 Page - Exar Corporation |
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XRT16C854 Datasheet(HTML) 13 Page - Exar Corporation |
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13 / 54 page  xr XR16C854/854D REV. 3.0.1 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO 13 2.9 Crystal Oscillator or External Clock Input The 854 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for all four UART sections in the device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see “Programmable Baud Rate Generator.” FIGURE 5. TYPICAL OSCILATOR CONNECTIONSL The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 5). Typical standard crystal frequencies are: 1.8432, 3.6864, 7.3728, 14.7456, 18.432, and 22.1184 MHz. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 5. For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site. 2.10 Programmable Baud Rate Generator Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The clock output of the prescaler goes to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. Table 6 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for DLL/DLM with the following equation. TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D PINS FCR BIT-0=0 (FIFO DISABLED) FCR BIT-0=1 (FIFO ENABLED) FCR Bit-3 = 0 (DMA Mode Disabled) FCR Bit-3 = 1 (DMA Mode Enabled) RXRDY# 0 = 1 byte 1 = no data 0 = at least 1 byte in FIFO 1 = FIFO empty 1 to 0 transition when FIFO reaches the trigger level, or timeout occurs. 0 to 1 transition when FIFO empties. TXRDY# 0 = THR empty 1 = byte in THR 0 = FIFO empty 1 = at least 1 byte in FIFO 0 = FIFO has at least 1 empty location. 1 = FIFO is full. divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16) C1 22-47pF C2 22-47pF 14.7456 MHz XTAL1 XTAL2 R=300K to 400K |
Similar Part No. - XRT16C854 |
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Similar Description - XRT16C854 |
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