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XRT72L52IQ Datasheet(PDF) 8 Page - Exar Corporation |
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XRT72L52IQ Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 480 page  XRT72L52 xr REV. 1.0.1 TWO CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER VI TX DS3 F-BIT MASK2 REGISTER, ADDRESS = 0X37.................................................................................178 TX DS3 F-BIT MASK3 REGISTER, ADDRESS = 0X38.................................................................................178 TX DS3 F-BIT MASK4 REGISTER, ADDRESS = 0X39.................................................................................178 4.2.5 The Transmit DS3 Line Interface Block................................................................................................ 178 Figure 53. Interfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU ............................................... 179 Figure 54. The Transmit DS3 LIU Interface block......................................................................................................... 179 Figure 55. The Behavior of TxPOS and TxNEG signals during data transmission while the Transmit DS3 LIU Interface is operating in the Unipolar Mode...................................................................................................................... 180 I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................180 TABLE 29: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE UNI I/O CONTROL REGISTER AND THE TRANSMIT DS3 FRAMER LINE INTERFACE OUTPUT MODE ................................................................... 181 Figure 56. Illustration of AMI Line Code........................................................................................................................ 181 Figure 57. Illustration of two examples of B3ZS Encoding ........................................................................................... 182 I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................182 TABLE 30: THE RELATIONSHIP BETWEEN BIT 4 (AMI/B3ZS*) WITHIN THE I/O CONTROL REGISTER AND THE BIPOLAR LINE CODE THAT IS OUTPUT BY THE TRANSMIT DS3 LIU INTERFACE BLOCK........................................................................ 182 I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................183 TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ............................................................. 183 Figure 58. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to be updated on the rising edge of TxLineClk .................................................................................................. 183 Figure 59. Waveform/Timing Relationship between TxLineClk, TxPOS and TxNEG - TxPOS and TxNEG are configured to be updated on the falling edge of TxLineClk ................................................................................................. 184 4.2.6 Transmit Section Interrupt Processing ................................................................................................. 184 BLOCK INTERRUPT ENABLE REGISTER (ADDRESS = 0X04)........................................................................184 TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .....................................185 TRANSMIT DS3 FEAC CONFIGURATION & STATUS REGISTER (ADDRESS = 0X31) .....................................185 TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .....................................................186 TXDS3 LAPD STATUS AND INTERRUPT REGISTER (ADDRESS = 0X34) .....................................................186 4.3 THE RECEIVE SECTION OF THE XRT72L52 (DS3 MODE OPERATION) ............................................................... 187 Figure 60. The XRT72L52 Receive Section configured to operate in the DS3 Mode................................................... 187 4.3.1 The Receive DS3 LIU Interface Block .................................................................................................. 187 Figure 61. The Receive DS3 LIU Interface Block ......................................................................................................... 188 Figure 62. Behavior of the RxPOS, RxNEG and RxLineClk signals during data reception of Unipolar Data ............... 188 I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................189 TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 3 (UNIPOLAR/BIPOLAR) WITHIN THE I/O CONTROL REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON....................................................... 189 Figure 63. IInterfacing the XRT72L52 Framer IC to the XRT73L00 DS3/E3/STS-1 LIU .............................................. 189 Figure 64. AMI Line Code ............................................................................................................................................. 190 Figure 65. Illustration of two examples of B3ZS Decoding ........................................................................................... 191 I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................191 TABLE 33: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REGISTER, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ..................................................................................................... 192 Figure 66. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be sampled on the rising edge of RxLineClk ...................................................................................................... 192 Figure 67. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and RxNEG are to be sampled on the falling edge of RxLineClk ..................................................................................................... 192 4.3.2 The Receive DS3 Framer Block ........................................................................................................... 193 Figure 68. The Receive DS3 Framer Block and the Associated Paths to Other Functional Blocks ............................. 193 Figure 69. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Maintenance Algorithm194 RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) .....................................................195 TABLE 34: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3 CONFIGURATION AND STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA ......................................................... 195 RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) .....................................................196 TABLE 35: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER BLOCK 196 RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) .....................................................196 TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIGURATION AND STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE DS3 FRAMER BLOCK ............................................................................................................................................................. 196 RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) .....................................................197 |
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