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XR17V252 Datasheet(PDF) 10 Page - Exar Corporation |
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XR17V252 Datasheet(HTML) 10 Page - Exar Corporation |
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10 / 69 page  XR17V252 10 66 MHZ PCI BUS DUAL UART WITH POWER MANAGEMENT SUPPORT REV. 1.0.1 NOTE: RWR=Read/Write from AD[31:0]. RO= Read Only. RWC=Read/Write-Clear. 1.2.1 Power States and Power State Transitions of the V252 The XR17V252 supports D0, D3hot and D3cold power states and is capable of generating the PME# signal from the D3hot state. The following paragraphs describe these power states and Figure 4 shows the power state transitions of the V252. D0 STATE The XR17V252 must be placed in the D0 state before being used in a system. The D0 state represents two states - D0 Uninitalized and D0 Active. Upon entering D0 from power up or transition from D3hot, the V252 will be in the D0 Uninitialized state. Once initialized by the system software, the V252 will enter the D0 Active state. In the D0 Active state, the V252 is fully functional and will respond to all PCI bus transactions as well as issue interrupts (INTA#). The system software can program the V252 to enter the D3hot state from the D0 state. D3 HOT STATE The V252 enters the D3hot state when the system software programs the V252 from D0 to D3hot. In this state, the V252 will not be fully functional. The V252 will respond only to PCI configuration space accesses, if a PCI clock is provided and will not respond to PCI memory accesses nor will it issue interrupts. However, the V252 will continue to receive data and the automatic software and hardware flow control, if enabled, will continue to function normally. While in the D3hot state, the V252 asserts the PME# (Power Management Event) signal, if enabled by setting PME_Enable bit, upon one of the following events: ■ RX pin of any of the channels goes LOW (START bit detected), or ■ Any of the delta bits of modem inputs (MSR register bits [3:0]) is set in any of the 2 channels (see page 48) The V252 also sets the PME_Status bit when such an event occurs, regardless of whether the PME_Enable bit is set or not. The system software can reset the PME_Status bit by writing a ’1’ to it. When the system software programs the V252 from D3hot to D0, typically in response to the PME# signal, the V252 enters the D0 Active state and will retain all the values of its internal registers. The V252 will keep its PCI signal drivers disabled for the duration of the D3hot to D0 Uninitialized state transition. The V252 saves the PME context (configuration registers and functional state information) in the D3hot state. Note: The V252 has a sleep mode which keeps the power consumption to a minimum (see Sleep Mode description on page 20). This is independent of the power state the V252 is in. The user can optionally place the V252 in sleep mode (via the software driver) in the Active D0 state anytime or specifically when the system software commands the V252 to enter the D3hot state. The crystal oscillator shuts down when the conditions given in Sleep Mode section on page 20 are satisfied, and re-starts when one of the events as described in the same section occurs. Upon re-starting, the oscillator may take a long time to settle. This time may be more than 20ms which is the maximum wait time guaranteed by the system software before resuming normal PCI bus transactions in the Active D0 state. Therefore, there may be data errors if the V252 is commanded to transmit data before the oscillator is ready. It is recommended not to use sleep mode while in the D3hot state for this reason. 14:9 RO Reserved 00000b 8 RWR PME_Enable 0b 7:2 RO Reserved 000000b 1:0 RWR PowerState 00b TABLE 2: POWER MANAGEMENT REGISTERS ADDRESS OFFSET BITS TYPE DESCRIPTION RESET VALUE (HEX OR BINARY) |
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