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XR16V2752IL32 Datasheet(PDF) 3 Page - Exar Corporation |
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XR16V2752IL32 Datasheet(HTML) 3 Page - Exar Corporation |
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3 / 51 page  PRELIMINARY XR16V2752 3 REV. P1.0.0 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PIN DESCRIPTIONS Pin Description NAME 32-QFN PIN # 44-PLCC PIN # TYPE DESCRIPTION DATA BUS INTERFACE A2 A1 A0 7 6 3 15 14 10 I Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during a data bus transaction. D7 D6 D5 D4 D3 D2 D1 D0 2 1 32 31 30 29 28 27 9 8 7 6 5 4 3 2 I/O Data bus lines [7:0] (bidirectional). IOR# 14 24 I Input/Output Read Strobe (active low). The falling edge instigates an inter- nal read cycle and retrieves the data byte from an internal register pointed to by the address lines [A2:A0]. The data byte is placed on the data bus to allow the host processor to read it on the rising edge. IOW# 11 20 I Input/Output Write Strobe (active low). The falling edge instigates an inter- nal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. CS# 10 18 I UART chip select (active low). This function selects channel A or B in accordance with the logical state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2752. CHSEL 8 16 I Channel Select - UART channel A or B is selected by the logical state of this pin when the CS# pin is a logic 0. A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A. Normally, CHSEL could just be an address line from the user CPU such as A4. Bit-0 of the Alternate Function Register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS# is low. It is especially useful during the ini- tialization routine. INTA 21 34 O UART channel A Interrupt output (active high). A logic high indicates chan- nel A is requesting for service. For more details, see Figures 17- 22. INTB 9 17 O UART channel B Interrupt output (active high). A logic high indicates chan- nel B is requesting for service. For more details, see Figures 17- 22. TXRDYA# - 1 O UART channel A Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel A. See Table 2. TXRDYB# - 32 O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See Table 2. MODEM OR SERIAL I/O INTERFACE TXA 23 38 O UART channel A Transmit Data or infrared encoder data. Standard trans- mit and receive interface is enabled when MCR[6] = 0. In this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW. If it is not used, leave it unconnected. |
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