HANBit

HMS1M32M8A/Z8A

HANBit Electronics Co.,Ltd.

7

Notes(Write Cycle)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among

/CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high.

6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of

opposite phase of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and

write cycle.

8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state.

10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output

should not be applied.

FUNCTIONAL DESCRIPTION

/CE

/WE

/OE

MODE

I/O PIN

SUPPLY CURRENT

H

X*

X

Not Select

High-Z

L

H

H

Output Disable

High-Z

LH

L

Read

L

L

X

Write

Note: X means Don't Care