TW9920
TECHWELL, INC.
46
REV. D
08/29/2005
0x08 – Vertical Delay Register, Low (VDELAY_LO)
Bit
Function
R/W
Description
Reset
7-0
VDELAY_
LO
R/W These bits are bit 7 to 0 of the 10-bit Vertical Delay register. The
two MSBs are in the CROP_HI register. It defines the number of
lines between the leading edge of VSYNC and the start of the
active video.
12
0x09 – Vertical Active Register, Low (VACTIVE_LO)
Bit
Function
R/W
Description
Reset
7-0
VACTIVE_
LO
R/W These bits are bit 7 to 0 of the 10-bit Vertical Active register. The
two MSBs are in the CROP_HI register. It defines the number of
active video lines per frame output.
The VACTIVE register has a shadow register for use with 50Hz
source when Atreg of Reg0x1C is not set. This register can be
accessed through the same index address by first changing the
format standard to any 50Hz standard.
F0
0x0A – Horizontal Delay Register, Low (HDELAY_LO)
Bit
Function
R/W
Description
Reset
7-0
HDELAY_
LO
R/W These bits are bit 7 to 0 of the 10-bit Horizontal Delay register. The
two MSBs are in the CROP_HI register. It defines the number of
pixels between the leading edge of the HSYNC and the start of the
image cropping for active video.
The HDELAY_LO register has two shadow registers for use with
PAL and SECAM sources respectively. These register can be
accessed using the same index address by first changing the
decoding format to the corresponding standard.
0F
0x0B – Horizontal Active Register, Low (HACTIVE_LO)
Bit
Function
R/W
Description
Reset
7-0
HACTIVE
_LO
R/W These bits are bit 7 to 0 of the 10-bit Horizontal Active register. The
two MSBs are in the CROP_HI register. It defines the number of
active pixels per line output.
D0
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