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HMD4M32M2VE Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd

Part No. HMD4M32M2VE
Description  16Mbyte(4Mx32) DRAM SIMM EDO MODE, 4K Refresh, 3.3V
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

HMD4M32M2VE Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd

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HANBit
HMD4M32M2VE
URL:www.hbe.co.kr
H ANBit Electronics Co.,Ltd.
REV.1.0 (August.2002)
4
ICC3 : /RAS Only Refresh Current * (/CAS=VIH, /RAS, Address cycling @tRC=min )
ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min )
ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V )
ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @tRC=min )
* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the
output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once
while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.
CAPACITANCE ( T
A=25
o
C, Vcc = 3.3V, f = 1Mz )
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Input Capacitance (A0-A11)
CIN1
-
10
pF
Input Capacitance (/W)
C IN2
-
14
pF
Input Capacitance (/RAS0, /RAS1)
CIN3
-
14
pF
Input Capacitance (/CAS0-/CAS3)
CIN4
-
14
pF
Input/Output Capacitance (DQ0-31)
CDQ1
-
14
pF
AC CHARACTERISTICS ( 0
o
C
≤ T
A ≤ 70
oC , Vcc = 3.3V±10%, See notes 1,2.)
-5
-6
STANDARD OPERATION
SYMBOL
MIN
MAX
MIN
MAX
UNIT
Random read or write cycle time
tRC
84
104
ns
Access time from /RAS
tRAC
50
60
ns
Access time from /CAS
tCAC
13
15
ns
Access time from column address
tAA
25
30
ns
/CAS to output in Low-Z
tCLZ
3
3
ns
Transition time (rise and fall)
tT
1
50
1
50
ns
/RAS precharge time
tRP
30
40
ns
/RAS pulse width
tRAS
50
10K
60
10K
ns
/RAS hold time
tRSH
13
15
ns
/CAS hold time
tCSH
38
45
ns
/CAS pulse width
tCAS
8
10K
10
10K
ns
/RAS to /CAS delay time
tRCD
20
37
20
45
ns
/RAS to column address delay time
tRAD
15
25
15
30
ns
/CAS to /RAS precharge time
tCRP
5
5
ns
Row address set-up time
tASR
0
0
ns
Row address hold time
tRAH
10
10
ns
Column address set-up time
tASC
0
0
ns


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