HMD1M32M2GL datasheet(6/7 Pages) HANBIT

Part #	HMD1M32M2GL

Description	4Mbyte(1Mx32) Fast Page Mode, 1K Refresh, 72Pin SIMM, 5V Design

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Manufacturer	HANBIT [Hanbit Electronics Co.,Ltd]

Direct Link	http://www.hbe.co.kr

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HANBit

HMD1M32M2GL

URL:www.hbe.co.kr

HANBit Electronics Co., Ltd.

REV.1.0 (August.2002)

6

the entire cycle. If tCWD >= tCWD (min), tRWD >= tRWD (min), TCPWD>= TCPWD(min), then the cycle is a read-modify-write

cycle and the data output will contain the data read from the selected address. If neither of the above conditions is

satisfied, the condition of the data out is indeterminate.

8. Either tRCH or tRRH must be satisfied for a read cycles.

9. These parameters are referenced to /CAS falling edge in early write cycles and to /WE falling edge in /OE controlled

write cycle and read-modify-write cycles.

10. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only,

if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA.

11. tASC, tCAH are are referenced to the earlier /CAS falling edge.

12. tCP is specified from the later /CAS rising edge in the previous cycle to the earlier /CAS falling edge in the next cycle.

13. tCWD is referenced to the later /CAS falling edge at word read-modify-write cycle.

14. tCWL is specified from /WE falling edge to the earlier /CAS rising edge .

15. tCSR is referenced to the earlier /CAS falling edge before /RAS transition low.

16. tCHR is referenced to the later /CAS rising edge after /RAS transition low.

PACKAGING INFORMATION

0.25 mm MAX

MIN

2.54 mm

1.27 mm

1.27

±0.08 mm

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