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DOM44S6V1G Datasheet(PDF) 5 Page - Hanbit Electronics Co.,Ltd |
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DOM44S6V1G Datasheet(HTML) 5 Page - Hanbit Electronics Co.,Ltd |
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5 / 29 page  HANBit HFDOM44S6Vxxx URL:www.hbe.co.kr 5 / 29 HANBit Electronics Co., Ltd. Rev. 1.0 (April, 2005) Signal Descriptions Table 2.2 Signal Descriptions Signal Name Dir. Pin Description A[2:0] I 33,35,36 In True IDE Mode only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. -PDIAG I/O 34 This input / output is the Pass Diagnostic signal in the Master / Slave handshake protocol. -DASP I/O 39 In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in the Master/Slave handshake protocol. -CS0, -CS1 I 37,38 CS0 is the chip select for the task file registers while CS2 is used to select the Alternate Status Register and the Device Control Register. D[15:00] I/O 3,4,5,6, 7,8,9,10, 11,12,13, 14,15,16, 17,18 All Task File operations occur in byte mode on the low order bus D00-D07 while all data transfers are 16 bit using D00-D15. GND -- 2,19,22, 24,26, 30,40,43 Ground. -IOR I 25 This is an I/O Read strobe generated by the host. -IOW I 23 The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the Storage Card controller registers when the Storage Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). IRQ O 31 In True IDE Mode signal is the active high Interrupt Request to the host. -RESET I 1 This input pin is the active low hardware reset from the host. IORDY O 27 This output signal may be used as IORDY. -IOIS16 O 32 This output signal is asserted low when this device is expecting a word data transfer cycle. VCC Power 41,42 Power |
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