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IDT72V70190 Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V70190 Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 20 page  11 COMMERCIALTEMPERATURERANGE IDT72V70190 3.3V TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256 ST-BUS F0i RX Stream 5717 drw05 Bit 7 Bit 7 CLK Bit 7 Bit 7 denotes the 3/4 point of the bit cell offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 GCI F0i Bit 0 Bit 0 CLK Bit 0 Bit 0 denotes the 3/4 point of the bit cell offset = 0, DLE = 0 offset = 1, DLE = 0 offset = 0, DLE = 1 offset = 1, DLE = 1 RX Stream RX Stream RX Stream RX Stream RX Stream RX Stream RX Stream TABLE 9 — OFFSET BITS (OFn2, OFn1, OFn0, DLEn) & FRAME DELAY BITS (FD11, FD2-0) Figure 5. Examples for Input Offset Delay Timing MeasurementResultfrom Corresponding InputStream Frame Delay Bits OffsetBits Offset FD11 FD2 FD1 FD0 OFn2 OFn1 OFn0 DLEn No clock period shift (Default) 1000000 0 + 0.5 clock period shift 0000000 1 + 1.0 clock period shift 1001001 0 + 1.5 clock period shift 0001001 1 + 2.0 clock period shift 1010010 0 + 2.5 clock period shift 0010010 1 + 3.0 clock period shift 1011011 0 + 3.5 clock period shift 0011011 1 + 4.0 clock period shift 1100100 0 + 4.5 clock period shift 0100100 1 |
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