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IDT72V70190 Datasheet(PDF) 6 Page - Integrated Device Technology

Part No. IDT72V70190
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 256 x 256
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V70190 Datasheet(HTML) 6 Page - Integrated Device Technology

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6
COMMERCIALTEMPERATURERANGE
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
Connection Memory
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
Channel 0
Channel 1
Channel 2
Channel 31
10000001
10000010
Data Memory
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Stream
Control Register
CRb7
5717 drw03
10000000
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 32 bytes are
randomly accessable via A0-A4 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CRb2 -CRb0.
CRb6CRb5CRb4CRb3CRb2CRb1CRb0
CRb2CRb1CRb0
0
1
CRb4
10011111
External Address Bits A7-A0
Figure 3. Addressing Internal Memories
CONNECTION MEMORY CONTROL
The CCO pin is a 4.096 Mb/s output, which carries 512 bits. The contents
of the CCO bit of each connection memory location are output on the CCO pin
once every frame. The contents of the CCO bits of the connection memory are
transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection
memory) and are synchronous with the data rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on the
serialstreams.
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
Theprocessorchannel(PC)bitoftheconnectionmemoryselectsbetween
Processor Mode and Connection Mode. If high, the contents of the connection
memoryareoutputontheTXstreams. Iflow,thestreamaddressbit(SAB)and
the channel address bit (CAB) of the connection memory defines the source
information(streamandchannel)ofthetime-slotthatwillbeswitchedtotheoutput
from data memory.
The
V/C(Variable/ConstantDelay)bitineachconnectionmemorylocation
allows the per-channel selection between variable and constant throughput
delay modes.
If the LPBK bit is high, the associated TX output channel data is internally
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70190
After power up, the state of the connection memory is unknown. As such,
theoutputsshouldbeputinhighimpedancebyholdingtheODElow. Whilethe
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.


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