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AS1100PE-Z Datasheet(PDF) 3 Page - ams AG |
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AS1100PE-Z Datasheet(HTML) 3 Page - ams AG |
3 / 12 page Data Sheet AS1100 Revision 1.32, Oct. 2004 Page 3 of 12 Parameter Symbol Conditions Min Typ Max Units Input Current DIN, CLK, LOAD IIH, IIL VIN = 0V or VDD -1 1 µA Logic High Input Voltage VIH 3.5 V Logic Low Input Voltage VIL 0.8 V Output High Voltage VOH DOUT, ISOURCE = -1mA VDD - 1 V Output Low Voltage VOL DOUT, ISINK = 1.6mA 0.4 V Hysteresis Voltage VI DIN, CLK, LOAD 1 V Timing Characteristics CLK Clock Period tCP 100 ns CLK Pulse Width High tCH 50 ns CLK Pulse Width Low tCL 50 ns CLK Rise to LOAD Rise Hold Time tCSH 0ns DIN Setup Time tDS 25 ns DIN Hold Time tDH 0ns Output Data Propagation Delay tDO CLOAD = 50pF 25 ns LOAD Rising Edge to Next Clock Rising Edge tLDCK 50 ns Minimum LOAD Pulse High tCSW 50 ns Data-to-Segment Delay tDSPD 2.25 ms Pin Description Pin Name Function 1 DIN Data input. Data is programmed into the 16Bit shift register on the rising CLK edge 2, 3, 5–8, 10, 11 DIG 0–DIG 7 8 digit driver lines that sink the current from the common cathode of the display. In shutdown mode the AS1100 switches the outputs to VDD 4, 9 GND both GND pins must be connected 12 LOAD Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into the register. 13 CLK Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial data is clocked into the internal shift register with the rising edge of the CLK signal. On the DOUT pin the data is applied with the falling edge of CLK. 14–17, 20–23 SEG A–G, DP Seven segment driver lines including the decimal point. When a segment is turned off the output is connected to GND. 18 ISET The current into ISET determines the peak current through the segments and therefore the brightness. 19 VDD Positive Supply Voltage (+5V) 24 DOUT Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The output is never set to high impedance. |
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