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MAX1276 Datasheet(PDF) 4 Page - Maxim Integrated Products

Part No. MAX1276
Description  1.8Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs with Internal Reference
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1276 Datasheet(HTML) 4 Page - Maxim Integrated Products

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1.8Msps, Single-Supply, Low-Power, True-
Differential, 12-Bit ADCs with Internal Reference
4
_______________________________________________________________________________________
Note 1: -40°C performance is guaranteed by design.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 3: No missing codes over temperature.
Note 4: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 5: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 6: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNVST. The IC idles in acquisition mode between conversions.
Note 7: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 8: Digital supply current is measured with the VIH level equal to VL, and the VIL level equal to GND.
TIMING CHARACTERISTICS
(VDD = +5V ±5%, VL = VDD, fSCLK = 28.8MHz, 50% duty cycle, TA = TMIN to TMAX, unless otherwise noted. Typical values are at
TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Pulse-Width High
tCH
VL = 1.8V to VDD
15.6
ns
SCLK Pulse-Width Low
tCL
VL = 1.8V to VDD
15.6
ns
CL = 30pF, VL = 4.75V to VDD
14
CL = 30pF, VL = 2.7V to VDD
17
SCLK Rise to DOUT Transition
tDOUT
CL = 30pF, VL = 1.8V to VDD
24
ns
DOUT Remains Valid After SCLK
tDHOLD
VL = 1.8V to VDD
4ns
CNVST Fall to SCLK Fall
tSETUP
VL = 1.8V to VDD
10
ns
CNVST Pulse Width
tCSW
VL = 1.8V to VDD
20
ns
Power-Up Time; Full Power-Down
tPWR-UP
2ms
Restart Time; Partial Power-Down
tRCV
16
Cycles
CNVST
SCLK
DOUT
tDHOLD
tDOUT
tSETUP
tCSW
tCL
tCH
Figure 1. Detailed Serial-Interface Timing
GND
6k
CL
DOUT
DOUT
CL
GND
VL
a) HIGH-Z TO VOH, VOL TO VOH,
AND VOH TO HIGH-Z
b) HIGH-Z TO VOL, VOH TO VOL,
AND VOL TO HIGH-Z
6k
Figure 2. Load Circuits for Enable/Disable Times


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