273804-002 datasheet(29/82 Pages) INTEL

Part #	273804-002

Description	Ultra-Low Voltage Intel-R Celeron-R Processor (0.13 u in the Micro FC-BGA Package

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Manufacturer	INTEL [Intel Corporation]

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Ultra-Low Voltage Intel

® Celeron® Processor — 650 MHz and 400 MHz

Datasheet

29

Multiplying the bus clock frequency is necessary to increase performance while allowing for easier

distribution of signals within the system. Clock multiplication within the processor is provided by

the internal Phase Lock Loop (PLL), which requires constant frequency BCLK and BCLK# inputs.

During Reset or on exit from the Deep Sleep state, the PLL requires some amount of time to

acquire the phase of BCLK and BCLK#. This time is called the PLL lock latency, which is

specified in Section 3.6, AC timing parameters T18 and T47.

3.4

Maximum Ratings

Table 13 contains the ULV Intel

® Celeron® processor stress ratings. Functional operation at the

absolute maximum and minimum is neither implied nor ensured. The processor should not receive

a clock while subjected to these conditions. Functional operating conditions are provided in the AC

and DC tables. Extended exposure to the maximum ratings may affect device reliability. Although

the processor contains protective circuitry to resist damage from static electric discharge, you

should always take precautions to avoid high static voltages or electric fields.

Table 13. Ultra-Low Voltage Intel

® Celeron® Processor Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

TStorage

Storage Temperature

–40

85

° C

1

VCC(Abs) Supply Voltage with respect to VSS

–0.5

1.75

V

VCCT

System Bus Buffer Voltage with respect to VSS

–0.3

1.75

V

VIN GTL

System Bus Buffer DC Input Voltage with respect to VSS

–0.3

1.75

V

2, 3

VIN125

1.25 V Buffer DC Input Voltage with respect to VSS

–0.3

1.75

V

4

VIN15

1.5 V Buffer DC Input Voltage with respect to VSS

–0.3

2.0

V

5

VIN18

1.8 V Buffer DC Input Voltage with respect to VSS

–0.3

2.0

V

6

VIN20

2.0 V Buffer DC Input Voltage with respect to VSS

–0.3

2.4

V

7

VIN25

2.5 V Buffer DC Input Voltage with respect to VSS

–0.3

3.3

V

9

VINVID

VID ball/pin DC Input Voltage with respect to VSS

—3.465

V

8

IVID

VID Current

-0.3

3.6

mA

8

NOTES:

1. The shipping container is only rated for 65° C.

2. Parameter applies to the AGTL signal groups only. Compliance with both VIN GTL specifications is required.

3. The voltage on the AGTL signals must never be below –0.3 V or above 1.75 V with respect to ground.

4. Parameter applies to CLKREF, TESTHI, VTTPWRGD signals.

5. Parameter applies to CMOS, Open-drain, APIC, TESTLO and TAP bus signal groups only.

6. Parameter applies to PWRGOOD signal.

7. Parameter applies to PICCLK signal.

8. Parameter applies to each VID pin/ball individually.

9. Parameter applies to BCLK signal in Single Ended Clocking Mode.

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