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APL5330KAE-TRL Datasheet(PDF) 2 Page - Anpec Electronics Coropration |
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APL5330KAE-TRL Datasheet(HTML) 2 Page - Anpec Electronics Coropration |
2 / 17 page Copyright © ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 APL5330 www.anpec.com.tw 2 Ordering and Marking Information Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature. Pin Description PIN NAME I/O DESCRIPTION VIN I Main power input pin. Connect this pin to a voltage source and an input capacitor. The APL5330 provides current from VIN pin to VOUT pin by controlling the NPN pass transistor. GND O Signal ground. VCNTL I Power input pin for internal control circuitry. Connect this pin to a voltage source to provide a bias for the internal control circuitry. A bypass capacitor is usually connected near this pin. VREF I Reference voltage input and active-low shutdown control pin. Connect this pin to a resistor divider and a capacitor for soft-start and filtering noise purposes. Pulling and holding the voltage on this pin low by an open-drain transistor shuts down the output. VOUT O Output pin of the regulator. Connect this pin to load. Output capacitors connected to this pin improves stability and transient response. The output voltage tracks the reference voltage, and the output pin provides the maximum current up to 2A. ° Block Diagram Package Code K : SOP-8 KA : SOP-8-P Operating Ambient Temp. Range E : -20 to 70 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APL5330 APL5330 XXXXX APL5330KE-TR : APL5330KAE-TR : XXXXX - Date Code Handling Code Temp. Range Package Code Lead Free Code GND VOUT VIN VCNTL VREF Current Limit Thermal Limit Voltage Regulation Shutdown |
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