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PRELIMINARY
CY2SSTU877
Document #: 38-07575 Rev. *B
Page 3 of 9
Absolute Maximum Conditions
Parameter
Description
Condition
Min.
Max.
Unit
VIN
Input Voltage Range
–0.5
VDDQ + 0.5
V
VOUT
Output Voltage Range
–0.5
VDDQ + 0.5
V
TS
Storage Temperature
–65
150
°C
VCC
Supply Voltage Range
–0.5
2.5
V
IIK
Input Clamp Current
–50
50
mA
IOK
Output Clamp Current
–50
50
mA
IO
Continuous Output Current
–50
50
mA
Continuous Current through VDD/GND
–100
100
mA
DC Electrical Specifications
Parameter
Description
Conditions
Min.
Max.
Unit
VIX
Input Differential Crossing Voltage
(VDDQ/2) – 0.15
(VDDQ/2) + 0.15
V
VID DC
Input Differential Voltage (DC Values)
0.3
VDDQ + 0.4
V
VID AC
Input Differential Voltage (AC Values)
0.6
VDDQ + 0.4
V
VIL
Input Low Voltage
(OE, OS, CK, CK#)
0.35 * VDDQ
V
VIH
Input High Voltage
(OE, OS, CK, CK#)
0.65 * VDDQ
V
VOL
Output Low Voltage
IOL = 100 µA0.1
V
IOL = 9 mA
0.6
V
VOH
Output High Voltage
IOH = –100 µAVDDQ – 0.2
V
IOH = –9 mA
1.1
V
IOH
Output High Current
–9
mA
IOL
Output Low Current
9
mA
VIK
Input Clamping Voltage
II = –18 mA
–1.2
V
VOD
Output Differential Voltage
0.5
V
VOX
Output Differential Crossing Voltage
VDDQ/2 – 0.08
VDDQ/2 + 0.08
V
AC Electrical Specifications
Parameter
Description
Conditions
Min.
Max.
Unit
SLR(O)
Output Slew Rate
Y[0:9], Y#[0:9], FBOUT,
FBOUT#
1.5
3
V/ns
SLR(I)
Input Slew Rate
CLK, CLK#, FBIN, FBIN#
1
4
V/ns
OE
0.5
V/ns
CIN
Input Capacitance
(Input Capacitance of CK, CK#,
FBIN, FBIN#) Vi = VDDQ or
GND
23
pF
COUT
pF
CIN(DELTA)
Ci(delta) (CK, CK#, FBIN,
FBIN#) Vi = VDDQ or GND
–0.25
0.25
pF
AC Timing Specifications
Parameter
Description
Conditions
Min.
Max.
Unit
FCLK
Clock Frequency
125
500
MHz
TDC
Duty Cycle
40
60
%
TLOCK
PLL Lock Time
–
10
µs
Tjitt (cc)
Cycle-to-cycle jitter
–30
30
ps
Tjit (Period)
Period Cycle-to-cycle jitter
–40
20
ps