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PEEL22LV10AZ Datasheet(PDF) 3 Page - Anachip Corp

Part No. PEEL22LV10AZ
Description  CMOS Programmable Electrically Erasable Logic Device
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Manufacturer  ANACHIP [Anachip Corp]
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Anachip Corp.
Rev. 1.0 Dec 16, 2004
Function Description
The PEEL™22LV10AZ implements logic functions as sum-of-
products expressions in a programmable-AND/fixed-OR logic
array. User-defined functions are created by programming the
connections of input signals into the array. User-configurable
output structures in the form of I/O macrocells further increase
logic flexibility.
Architecture Overview
The PEEL™22LV10AZ architecture is illustrated in the block
diagram of Figure 26. Twelve dedicated inputs and 10 I/Os pro-
vide up to 22 inputs and 10 outputs for creation of logic func- tions.
At the core of the device is a programmable electrically- erasable
AND array that drives a fixed OR array. With this struc- ture, the
PEEL™22LV10AZ can implement up to 10 sum-of- products
logic expressions.
Associated with each of the ten OR functions is an I/O macrocell
that can be independently programmed to one of 12 different
configurations, including the four standard 22V10 modes. The
programmable macrocells allow each I/O to be used to create
sequential or combinatorial logic functions of active-high or
active-low polarity, while providing three different feedback
paths into the AND array.
AND/OR Logic Array
The programmable AND array of the PEEL™22LV10AZ
(shown in Figure 3) is formed by input lines intersecting product
terms. The input lines and product terms are used as follows:
44 Input Lines:
– 24 input lines carry the true and complement of the signals
applied to the 12 input pins
– 20 additional lines carry the true and complement values of
feedback or input signals from the 10 I/Os
133 Product Terms:
– 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and
16) are used to form sum of product functions
– 10 output enable terms (one for each I/O)
– 1 global synchronous preset term
– 1 global asynchronous clear term
– 1 programmable clock term
At each input-line/product-term intersection, there is an
EEPROM memory cell that determines whether or not there is a
logical connection at that intersection. Each product term is
essentially a 44-input AND gate. A product term that is con-
nected to both the true and complement of an input signal will
always be FALSE and thus will not affect the OR function that it
drives. When all the connections on a product term are opened, a
“don’t care” state exists and that term will always be TRUE. When
programming the PEEL™22LV10AZ, the device pro- grammer
first performs a bulk erase to remove the previous pat- tern. The
erase cycle opens every logical connection in the array. The device
is configured to perform the user-defined function by
programming selected connections in the AND array. (Note that
PEEL™ device programmers automatically program all of the
connections on unused product terms so that they will have no
effect on the output function).
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides com-
3plete control over the architecture of each output. The ability to
configure each output independently lets you to tailor the config-
uration of the PEEL™22LV10AZ to the precise requirements of
your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 27, consists of a D-type
flip-flop and two signal-select multiplexers. The configuration of
each macrocell is determined by the four EEPROM bits control-
ling these multiplexers. These bits determine output polarity, out-
put type (registered or non-registered) and input-feedback path
(bidirectional I/O, combinatorial feedback). Refer to Table 1 for
Equivalent circuits for the twelve macrocell configurations are
illustrated in Figure 1. In addition to emulating the four PAL-type
output structures (configurations 3, 4, 9, and 10), the macrocell
provides eight additional configurations. When creating a
PEEL™ device design, the desired macrocell configuration is
generally specified explicitly in the design file. When the design is
assembled or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming file.
Output Type
The signal from the OR array can be fed directly to the output pin
(combinatorial function) or latched in the D-type flip-flop (regis-
tered function). The D-type flip-flop latches data on the rising
edge of the clock and is controlled by the global preset and clear
terms. When the synchronous preset term is satisfied, the Q out-
put of the register is set HIGH at the next rising edge of the clock
input. Satisfying the asynchronous clear sets Q LOW, regardless of
the clock state. If both terms are satisfied simultaneously, the clear
will override the preset.
Output Polarity
Each macrocell can be configured to implement active-high or
active-low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled
under the control of its associated programmable output enable
product term. When the logical conditions programmed on the
output enable term are satisfied, the output signal is propagated to
the I/O pin. Otherwise, the output buffer is switched into the
high-impedance state.
Under the control of the output enable term, the I/O pin can func-
tion as a dedicated input, a dedicated output, or a bi-directional I/ O.
Opening every connection on the output enable term will per-
manently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will

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