Connection Diagrams

8 Lead PSOP Package (MRA)

8 Lead LLP Surface Mount Package (SD)

20120930

Top View

See NS Package Number MRA08A

20120950

Top View

See NS Package Number SDC08A

Ordering Information

TABLE 1. Package Marking and Ordering Information

Output Voltage

Grade

Order Information

Supplied as:

ADJ

STD

LP3878MR-ADJ

95 Units per Rail

ADJ

STD

LP3878MRX-ADJ

2500 Units on Tape and Reel

ADJ

STD

LP3878SD-ADJ

1000 Units on Tape and Reel

ADJ

STD

LP3878SDX-ADJ

4500 Units on Tape and Reel

Pin Description

PIN

NAME

FUNCTION

1

BYPASS

The capacitor connected between BYPASS and GROUND lowers

output noise voltage level and is required for loop stability.

2

N/C

DO NOT CONNECT. This pin is used for post package test and must

be left floating.

3

GROUND

Device ground.

4

INPUT

Input source voltage.

5

OUTPUT

Regulated output voltage.

6

ADJ

Provides feedback to error amplifier from the resistive divider that sets

the output voltage.

7

N/C

No internal connection.

8

SHUTDOWN

Output is enabled above turn-on threshold voltage. Pull down to turn off

regulator output.

PSOP, LLP

DAP

SUBSTRATE

GROUND

The exposed die attach pad should be connected to a thermal pad at

ground potential. For additional information on using National

Semiconductor’s Non Pull Back LLP package, please refer to LLP

application note AN-1187

www.national.com

2