Clocked 512 x 9, 2K x 9 FIFOs
CY7C441
CY7C443
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-06032 Rev. *A
Revised December 26, 2002
43
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 512 x 9 (CY7C441)
• 2,048 x 9 (CY7C443)
• 0.65 micron CMOS for optimum speed/power
• High-speed 83-MHz operation (12 ns read/write cycle
time)
• Low power — ICC=70 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Almost Empty, and Almost Full status flags
• TTL compatible
• Parity generation/checking
• Independent read and write enable pins
• Supports free-running 50% duty cycle clock inputs
• Center power and ground pins for reduced noise
• Width Expansion Capability
• Available in PLCC packages
Functional Description
The CY7C441 and CY7C443 are high-speed, low-power,
first-in first-out (FIFO) memories with clocked read and write
interfaces. Both FIFOs are 9 bits wide. The CY7C441 has a
512 word by 9 bit memory array, while the CY7C443 has a
2048 word by 9 bit memory array. These devices provide so-
lutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
Both FIFOs have 9-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (CKW) and a write enable
pin (ENW). When ENW is asserted, data is written into the
FIFO on the rising edge of the CKW signal. While ENW is held
active, data is continually written into the FIFO on each CKW
cycle. The output port is controlled in a similar manner by a
free-running read clock (CKR) and a read enable pin (ENR).
The read (CKR) and write (CKW) clocks may be tied together
for single-clock operation or the two clocks may be run inde-
pendently for asynchronous read/write applications. Clock fre-
quencies up to 83.3 MHz are acceptable.
The CY7C441 and CY7C443 clocked FIFOs provide two sta-
tus flag pins (F1 and F2). These flags are decoded to deter-
mine one of four states: Empty, Almost Empty, Intermediate,
and Almost Full (Table 1). The flags are synchronous; i.e.,
change state relative to either the read clock (CKR) or the write
clock (CKW). The Empty and Almost Empty states are updat-
ed exclusively by the CKR while Almost Full is updated exclu-
sively by CKW. The synchronous flag architecture guarantees
that the flags maintain their status for some minimum time.
The CY7C441 and the CY7C443 use center power and
ground for reduced noise. Both configurations are fabricated
using an advanced.65
µm CMOS technology. Input ESD pro-
tection is greater than 2001V, and latch-up is prevented by
reliable layout techniques and guard rings.
Logic Block Diagram
Pin Configuration
C441-1
C441-2
12
31
4
5
6
7
8
9
10
32 1
30
13
14 15 16 17
26
25
24
23
22
21
11
Top View
PLCC
1819 20
27
28
29
32
7C443
7C441
D7
D8
NC
MR
VSS
CKR
ENR
Q8
Q7
D0
ENW
CKW
VCC
VSS
F1
F2
NC
Q0
D0– 8
CKW
ENW
MR
Q0– 8
ENR
CKR
F1
F2
INPUT
REGISTER
RAM
ARRAY
512 x 9
2048x 9
OUTPUT
REGISTER
READ
CONTROL
LOGIC
FLAG
LOGIC
WRITE
CONTROL
LOGIC
RESET
LOGIC
READ
POINTER
WRITE
POINTER
D1 D2 D3 NCD 4 D5 D6
Q1 Q2
NC
Q3
Q4 Q5 Q6
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