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ACEX1K Datasheet(PDF) 10 Page - Altera Corporation |
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ACEX1K Datasheet(HTML) 10 Page - Altera Corporation |
10 / 86 page 10 Altera Corporation ACEX 1K Programmable Logic Device Family Data Sheet Figure 2. ACEX 1K Device in Dual-Port RAM Mode Note (1) Notes: (1) All registers can be asynchronously cleared by EAB local interconnect signals, global signals, or the chip-wide reset. (2) EP1K10, EP1K30, and EP1K50 devices have 88 EAB local interconnect channels; EP1K100 devices have 104 EAB local interconnect channels. The EAB can use Altera megafunctions to implement dual-port RAM applications where both ports can read or write, as shown in Figure 3. The ACEX 1K EAB can also be used in a single-port mode (see Figure 4). Column Interconnect EAB Local Interconnect (2) Dedicated Clocks 24 D ENA Q D ENA Q D ENA Q D ENA Q D ENA Q data[ ] rdaddress[ ] wraddress[ ] RAM/ROM 256 × 16 512 × 8 1,024 × 4 2,048 × 2 Data In Read Address Write Address Read Enable Write Enable Data Out 4, 8, 16, 32 4, 8, 16, 32 outclocken inclocken inclock outclock D ENA Q Write Pulse Generator rden wren Multiplexers allow read address and read enable registers to be clocked by inclock or outclock signals. Row Interconnect 4, 8 Dedicated Inputs & Global Signals |
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