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MC74VHC1GT02 Datasheet(PDF) 1 Page - E-Tech Electronics LTD

Part No. MC74VHC1GT02
Description  2-Input NOR Gate / CMOS Logic Level Shifter
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Maker  ETL [E-Tech Electronics LTD]
Homepage  http://e-tech.com.hk
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MC74VHC1GT02 Datasheet(HTML) 1 Page - E-Tech Electronics LTD

   
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VHT2–1/4
VJd
MC74VHC1GT02
VJd
1
3
2
4
5
TSOP–5/SOT–23/SC–59
DT SUFFIX
CASE 483
The MC74VHC1GT02 is a single gate 2–input NOR fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHC1GT02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT02 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: tPD = 4.7 ns (Typ) at VCC = 5 V
SC–88A / SOT–353/SC–70
DF SUFFIX
CASE 419A
1
3
2
4
5
MARKING DIAGRAMS
Pin 1
d = Date Code
Pin 1
d = Date Code
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
PIN ASSIGNMENT
1
IN B
2
IN A
3
GND
4
OUT Y
5V CC
FUNCTION TABLE
Inputs
Output
AB
Y
LL
H
LH
L
HL
L
HH
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
2-Input NOR Gate / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• CMOS–Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.
1 VCC @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 65; Equivalent Gates = 14
Y


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