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HDD16M64D8W-10A Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd

Part # HDD16M64D8W-10A
Description  DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM,
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

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HANBit
HDD16M64D8W
URL : www.hbe.co.kr
4
HANBit Electronics Co.,Ltd.
REV 2.0 (November.2002)
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNTE
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage temperature
TSTG
-55 ~ +150
°C
Power dissipation
PD
8.0
W
Short circuit current
IOS
50
mA
Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) )
PARAMETER
SYMBOL
MIN
MAX
UNIT
NOTE
Supply Voltage
VDD
2.3
2.7
V
I/O Supply Voltage
VDDQ
2.3
2.7
V
I/O Reference Voltage
VREF
VDDQ/2-50mV
VDDQ/2+50mV
V
1
I/O Termination Voltage(system)
VTT
VREF – 0.04
VREF + 0.04
V
2
Input High Voltage
VIH (DC)
VREF + 0.15
VREF + 0.3
V
4
Input Low Voltage
VIL (DC)
-0.3
VREF - 0.15
V
4
Input Voltage Level, CK and /CK inputs
VIN (DC)
-0.3
VDDQ + 0.3
V
Input Differential Voltage, CK and /CK inputs
VID (DC)
0.3
VDDQ + 0.6
V
3
Input crossing point voltage, CK and CK inputs
VIx (DC)
1.15
1.35
V
5
Input leakage current
I LI
-2
2
uA
Output leakage current
I OZ
-5
5
uA
Output High current (VOUT = 1.95V)
I OH
-16.8
mA
Output Low current (VOUT = 0.35V)
I OL
16.8
mA
Output High Current(Half strengh driver)
IOH
-9
mA
Output High Current(Half strengh driver)
IOL
9
mA
Notes
1. Includes
± 25mV margin for DC offset on V
REF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF,
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on
VREF and internal DRAM noise coupled
TO
VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH.
2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to
VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
simulation. The AC and DC input specifications are relative to a
VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.
6. These charactericteristics obey the SSTL-2 class II standards.


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