SRAM TYPE FIFO MEMORY

M66850J/FP, M66851J/FP

M66852J/FP, M66853J/FP

MITSUBISHI <DIGITAL ASSP>

Write Clock to Almost-Full Flag

Read Clock to Empty Flag

25

Clock Cycle Time

ns

ns

ns

ns

SWITCHING CHARACTERISTICS (Ta=0 – 70˚C, Vcc=5V

±10%, GND=0V)

Limits

Min.

Typ.

Max.

Symbol

Unit

Parameter

15

Data Access Time

Write Clock to Full Flag

3

0

3

ns

TIMING CONDITIONS (Ta=0 – 70˚C, Vcc=5V

±10%, GND=0V)

Limits

Min.

Typ.

Max.

Symbol

Unit

Parameter

Clock Pulse Width HIGH

Clock Pulse Width LOW

Data Setup Time

Data Hold Time

Enable Setup Time

Enable Hold Time

Reset Pulse Width

Reset Setup Time

Skew time between Read Clock and Write Clock for Empty Flag and Full Flag

Skew time between Read Clock and Write Clock for Almost-Empty Flag and Almost-Full

Flag

10

10

6

1

6

1

25

25

25

10

40

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Read Clock to Almost-Empty Flag

Output Enable to Output Valid

Output Enable to Output in Low-Z

Output Enable to Output in High-Z

Reset to Flag and Output Valid time

ns

ns

ns

ns

ns

3

15

15

15

15

13

13

25

Reset Recovery Time

AC TEST CONDITIONS

In Pulse Levels

GND – 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 4

D.U.T.

1.1k

Ω

30pF

680

Ω

5.0V

Figure 4. Output Load

Including Test board and scope capacitances.

5