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MPC8540 Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc |
14 / 1302 page MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 xiv Freescale Semiconductor Contents Paragraph Number Title Page Number 9.4 Memory Map/Register Definition ................................................................................... 9-9 9.4.1 Register Descriptions ................................................................................................... 9-9 9.4.1.1 Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-10 9.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-10 9.4.1.3 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-11 9.4.1.4 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-13 9.4.1.5 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-14 9.4.1.6 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-16 9.4.1.7 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-16 9.4.1.8 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI) ............................................................................... 9-17 9.4.1.9 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO).............................................................................. 9-18 9.4.1.10 Memory Data Path Error Injection Mask ECC (ECC_ERR_INJECT)........................................................................................ 9-18 9.4.1.11 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-19 9.4.1.12 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-20 9.4.1.13 Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-20 9.4.1.14 Memory Error Detect (ERR_DETECT)................................................................ 9-21 9.4.1.15 Memory Error Disable (ERR_DISABLE)............................................................. 9-21 9.4.1.16 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-22 9.4.1.17 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-23 9.4.1.18 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-24 9.4.1.19 Single-Bit ECC Memory Error Management (ERR_SBE) ................................... 9-25 9.5 Functional Description................................................................................................... 9-25 9.5.1 DDR SDRAM Interface Operation............................................................................ 9-30 9.5.1.1 Supported DDR SDRAM Organizations ............................................................... 9-31 9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-31 9.5.3 JEDEC Standard DDR SDRAM Interface Commands ............................................. 9-32 9.5.4 SDRAM Interface Timing ......................................................................................... 9-34 9.5.4.1 Clock Distribution ................................................................................................. 9-38 9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-38 9.5.6 DDR SDRAM Registered DIMM Mode ................................................................... 9-39 9.5.7 DDR SDRAM Write Timing Adjustments ................................................................ 9-40 9.5.8 DDR SDRAM Refresh .............................................................................................. 9-41 9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-42 9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes ................................................ 9-43 9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-44 9.5.9 DDR Data Beat Ordering........................................................................................... 9-45 9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-45 |
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