MPC8540 datasheet(33/1302 Pages) FREESCALE

Part #	MPC8540

Description	MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xxxiii

Contents

Paragraph

Number

Title

Page

Number

17.3.1.13

Base Device ID Command and Status Register (BDIDCSR) ............................. 17-25

17.3.1.14

Host Base Device ID Lock Command and Status Register

(HBDIDLCSR)................................................................................................ 17-26

17.3.1.15

Component Tag Command and Status Register (CTCSR).................................. 17-26

17.3.1.16

8/16 LP-LVDS Port Maintenance Block Header 0 Command and

Status Register (PMBH0CSR)......................................................................... 17-27

17.3.1.17

Port Link Time-Out Control Command and Status Register

(PLTOCCSR)................................................................................................... 17-27

17.3.1.18

Port Response Time-Out Control Command and Status Register

(PRTOCCSR) .................................................................................................. 17-28

17.3.1.19

Port General Control Command and Status Register (PGCCSR) ....................... 17-29

17.3.1.20

Port Link Maintenance Request Command and Status Register

(PLMREQCSR)............................................................................................... 17-29

17.3.1.21

Port Link Maintenance Response Command and Status Register

(PLMRESPCSR) ............................................................................................. 17-30

17.3.1.22

Port Local AckID Status Command and Status Register (PLASCSR) ............... 17-31

17.3.1.23

Port Error and Status Command and Status Register (PESCSR) ........................ 17-31

17.3.1.24

Port Control Command and Status Register (PCCSR)........................................ 17-33

17.3.2

Implementation Registers ........................................................................................ 17-34

17.3.2.1

General Registers................................................................................................. 17-34

17.3.2.1.1

Configuration Register (CR) ........................................................................... 17-34

17.3.2.1.2

Port Configuration Register (PCR).................................................................. 17-35

17.3.2.1.3

Port Error Injection Register (PEIR) ............................................................... 17-35

17.3.2.2

ATMU Registers .................................................................................................. 17-36

17.3.2.2.1

RapidIO Outbound Window Translation Address Registers 0–8

(ROWTARn) ............................................................................................... 17-37

17.3.2.2.2

RapidIO Outbound Window Base Address Registers 1–8

(ROWBARn) ............................................................................................... 17-38

17.3.2.2.3

RapidIO Outbound Window Attributes Registers 0–8 (ROWARn)................ 17-39

17.3.2.2.4

RapidIO Inbound Window Translation Address Registers 0–4

(RIWTARn) ................................................................................................. 17-40

17.3.2.2.5

RapidIO Inbound Window Base Address Registers 1–4

(RIWBARn) ................................................................................................ 17-41

17.3.2.2.6

RapidIO Inbound Window Attributes Registers 0–4 (RIWARn) .................... 17-42

17.3.2.3

Error Management Registers ............................................................................... 17-43

17.3.2.3.1

Port Notification/Fatal Error Detect Register (PNFEDR) ............................... 17-44

17.3.2.3.2

Port Notification/Fatal Error Detect Disable Register

(PNFEDiR) .................................................................................................. 17-47

17.3.2.3.3

Port Notification/Fatal Error Interrupt Enable Register

(PNFEIER) .................................................................................................. 17-49

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