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M68EM11KW1 Datasheet(PDF) 55 Page - Motorola, Inc |
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M68EM11KW1 Datasheet(HTML) 55 Page - Motorola, Inc |
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55 / 238 page  MC68HC11KW1 MOTOROLA 4-11 OPERATING MODES AND ON-CHIP MEMORY 4 Refer to Table 4-4, which is a summary of mode pin operation, the mode control bits and the four operating modes. A normal mode is selected when MODB is logic one during reset. One of three reset vectors is fetched from address $FFFA–$FFFF, and program execution begins from the address indicated by this vector. If MODB is logic zero during reset, the special mode reset vector is fetched from addresses $BFFA–$BFFF and software has access to special test features. Refer to Section 5. 4.3.1.1 HPRIO — Highest priority I-bit interrupt & misc. register Note: RBOOT, SMOD and MDA bits depend on the power-up initialization mode and can only be written in special modes when SMOD = 1. Refer to Table 4-4. RBOOT — Read bootstrap ROM 1 (set) – Bootloader ROM enabled, at $BE40–$BFFF. 0 (clear) – Bootloader ROM disabled and not in map. SMOD — Special mode select 1 (set) – Special mode variation in effect. 0 (clear) – Normal mode variation in effect. Once cleared, cannot be set again. MDA — Mode select A 1 (set) – Normal expanded or special test mode. (Expanded buses active.) 0 (clear) – Normal single chip or special bootstrap mode. (Ports active.) PSEL[4:0] — Priority select bits (refer to Section 5) Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset Highest priority interrupt (HPRIO) $003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110 Table 4-4 Hardware mode select summary Inputs Mode Control bits in HPRIO (latched at reset) MODB MODA RBOOT SMOD MDA 1 0 Single chip 0 0 0 1 1 Expanded 0 0 1 0 0 Special bootstrap 1 1 0 0 1 Special test 0 1 1 TPG 53 |
Similar Part No. - M68EM11KW1 |
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Similar Description - M68EM11KW1 |
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