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M68EM11KW1 Datasheet(PDF) 54 Page - Motorola, Inc |
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M68EM11KW1 Datasheet(HTML) 54 Page - Motorola, Inc |
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54 / 238 page  MOTOROLA 4-10 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY 4 4.3 System initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. The following table lists registers that can be written only once after reset, or that must be written within the first 64 cycles after reset. 4.3.1 Mode selection The four mode variations are selected by the logic states of the mode A (MODA) and mode B (MODB) pins during reset. The MODA and MODB logic levels determine the logic state of the special mode (SMOD) and mode A (MDA) control bits in the highest priority I-bit interrupt and miscellaneous (HPRIO) register. After reset is released, the mode select pins no longer influence the MCU operating mode. In single chip operating mode, MODA pin is connected to a logic zero. In expanded mode, MODA is normally connected to VDD through a pull-up resistor of 4.7 kΩ. The MODA pin also functions as the load instruction register (LIR) pin when the MCU is not in reset. The open-drain active low LIR output pin drives low during the first E cycle of each instruction. The MODB pin also functions as the stand-by power input (VSTBY), which allows the RAM contents to be maintained in the absence of VDD. Table 4-3 Registers with limited write access Register address Register name Must be written in first 64 cycles Write once only $x024 Timer interrupt mask register 2 (TMSK2) (1) (1) When SMOD = 0, bits 1 and 0 can be written only once, during the first 64 cycles, after which they become read-only. When SMOD = 1, however, these bits can be written at any time. All other bits can be written at any time. — $x035 Block protect register (BPROT) (2) (2) Bits can be written to zero once and only in the first 64 cycles or in special modes. Bits can be set to one at any time. — $x037 EEPROM mapping register (INIT2) No Yes $x038 System configuration options register 2 (OPT2) No (3) (3) Bit 4 (IRVNE) can be written only once. $x039 System configuration options register (OPTION) (4) (4) When SMOD = 0, bits 5, 4, 2, 1, and 0 can be written once and only in the first 64 cycles. When SMOD = 1, however, bits 5, 4, 2, 1, and 0 can be written at any time. All other bits can be written at any time. — $x03D RAM and I/O map register (INIT) (5) (5) When SMOD = 0, bits can be written only once, during the first 64 cycles, after which the register becomes read-only.When SMOD = 1, bits can be written at any time. — $x081 Timer control register 4 (Timer 2) TCTL4 No (6) (6) Bits 5, 4, 3 and 2 can be written only once. $x091 Timer control register 6 (Timer 3) TCTL6 No (6) TPG 52 |
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