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M11L416256SA Datasheet(PDF) 5 Page - Elite Semiconductor Memory Technology Inc. |
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M11L416256SA Datasheet(HTML) 5 Page - Elite Semiconductor Memory Technology Inc. |
5 / 16 page EliteMT M11L416256SA (Continued) -35 PARAMETER SYMBOL MIN MAX UNIT NOTES Read Command Hold Time Reference to CAS tRCH 0 ns 9,15,19 Read Command Hold Time Reference to RAS tRRH 0 ns 9 CAS to Output in Low-Z tCLZ 3 ns 20 Output Buffer Turn-off Delay From CAS or RAS tOFF1 3 15 ns 10,17,20 Output Buffer Turn-off to OE tOFF2 8 ns 17,26 Write Command Setup Time tWCS 0 ns 11,15,18 Write Command Hold Time tWCH 5 ns 15,25 Write Command Hold Time(Reference to RAS ) tWCR 30 ns 15 Write Command Pulse Width tWP 5 ns 15 Write Command to RAS Lead Time tRWL 9 ns 15 Write Command to CAS Lead Time tCWL 7 ns 15,19 Data-in Setup Time tDS 0 ns 12,20 Data-in Hold Time tDH 5 ns 12,20 Data-in Hold Time (Reference to RAS ) tDHR 30 ns RAS to WE Delay Time tRWD 51 ns 11 Column Address to WE Delay Time tAWD 34 ns 11 CAS to WE Delay Time tCWD 26 ns 11,18 Transition Time (rise or fall) tT 2.5 50 ns 2,3 Refresh Period (512 cycles) tREF 8 ms RAS to CAS Precharge Time tRPC 10 ns CAS Setup Time(CBR REFRESH) tCSR 10 ns 1,18 CAS Hold Time(CBR REFRESH) tCHR 10 ns 1,19 OE Hold Time From WE During Read-Mode-Write Cycle tOEH 4 ns 16 OE Low to CAS High Setup Time tOES 4 ns OE High Hold Time From CAS High tOEHC 2 ns OE Precharge Time tOEP 2 ns OE Setup Prior to RAS During Hidden Refresh Cycle tORD 0 ns Last CAS Going Low to First CAS Returning High tCLCH 5 ns 21 Data Output Hold After CAS Returning Low tCOH 3 ns Output Disable Delay From WE tWHZ 3 7 ns Self Refresh RAS Low Pulse width tRASS 100 μ s 27,28 Self Refresh RAS High Precharge Time tRPS 65 ns 27,28 Self Refresh CAS Hold Time tCHS -50 ns 27,28 Elite Memory Technology Inc Publication Date: Aug. 2005 Revision : 1.4 5/16 |
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