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ICX405AL Datasheet(PDF) 3 Page - Sony Corporation

Part # ICX405AL
Description  Diagonal 6mm (Type 1/3) CCD Image Sensor for CCIR B/W Video Cameras
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

ICX405AL Datasheet(HTML) 3 Page - Sony Corporation

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ICX405AL
Bias Conditions
Clock Voltage Conditions
DC Characteristics
Item
Supply current
IDD
35
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
Item
Supply voltage
Protective transistor bias
Substrate clock
VDD
VL
φSUB
14.55
15.0
1
2
15.45
V
Symbol
Min.
Typ.
Max.
Unit
Remarks
1 V
L
setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Item
Readout clock voltage
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
V
φV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
V
φH
VHL
V
φRG
VRGLH – VRGLL
VRGL – VRGLm
VRGH
V
φSUB
14.55
–0.05
–0.2
–8.0
6.3
–0.25
–0.25
4.75
–0.05
4.5
VDD
+0.3
21.0
15.0
0
0
–7.0
7.0
5.0
0
5.0
VDD
+0.6
22.0
15.45
0.05
0.05
–6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
VDD
+0.9
23.5
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
4
5
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
V
φV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.1µF
capacitance
Low-level coupling
Low-level coupling
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Vertical transfer clock
voltage
Symbol
Min.
Typ.
Max.
Unit
Waveform
diagram
Remarks


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