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ICS8745BYLF Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS8745BYLF Datasheet(HTML) 1 Page - Integrated Circuit Systems |
1 / 15 page 8745BY www.icst.com/products/hiperclocks.html REV. B DECEMBER 2, 2004 1 Integrated Circuit Systems, Inc. ICS8745B 1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR GENERAL DESCRIPTION The ICS8745B is a highly versatile 1:5 LVDS Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8745B has a fully integrated PLL and can be configured as zero delay buffer, multi- plier or divider, and has an output frequency range of 31.25MHz to 700MHz. The Reference Divider, Feedback Divider and Output Divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8.The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output dividers. FEATURES • 5 differential LVDS outputs designed to meet or exceed the requirements of ANSI TIA/EIA-644 • Selectable differential clock inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration with configurable frequencies • Programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 • Cycle-to-cycle jitter: 30ps (maximum) • Output skew: 35ps (maximum) • Static phase offset: 25ps ± 125ps • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Lead-Free package fully RoHS compliant HiPerClockS™ ICS BLOCK DIAGRAM PIN ASSIGNMENT 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 Q3 nQ3 VDDO Q2 nQ2 GND Q1 nQ1 SEL0 SEL1 CLK0 nCLK0 CLK1 nCLK1 CLK_SEL MR ICS8745B PLL_SEL CLK0 nCLK0 CLK1 nCLK1 CLK_SEL FB_IN nFB_IN SEL0 SEL1 SEL2 SEL3 MR Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 0 1 PLL 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 ÷1, ÷2, ÷4, ÷8, ÷16, ÷32 , ÷64 |
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