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HD66503 Datasheet(PDF) 4 Page - Hitachi Semiconductor

Part No. HD66503
Description  (240-Channel Common Driver with Internal LCD Timing Circuit)
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Maker  HITACHI [Hitachi Semiconductor]
Homepage  http://www.renesas.com/eng
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HD66503 Datasheet(HTML) 4 Page - Hitachi Semiconductor

 
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HD66503
930
Classi-
fication
Symbol
Pin No.
Pin Name
I/O
Number
of Pins
Functions
Control
signals
CR, R, C
247
248
249
CR
R
C
3
These pins are used as shown in Figure
4 in master mode, and as shown in
Figure 5 in slave mode.
5(6(7
261
Reset
Input
1
The following initiation will be proceeded
by setting to initiation.
1) Stops the internal oscillator or the
external oscillator clock input.
2) Initializes the counters of the liquid
crystal display timing generator and
alternating signal (M) generator.
3) Set display off control output (
'2&)
to low and turns off display.
After reset, display off control output
(
'2&) will stay low for four more frame
cycles (four clocks of FLM signals) to
prevent error display at initiation. The
electrical characteristics are shown in
Table 4. See Figure 2.
However, when reset is performed
during operation, RAM data in the
HD66520 which is used together with
the HD66503 may be destroyed.
Therefore, write data to the RAM again.
LCD
timing
CL1
263
Clock 1
I/O
1
The bidirectional shift register shifts
data at the falling edge of CL1. During
master mode, this pin-outputs a data
transfer clock with a two times larger
cycle than the internal oscillator (or the
cycle of the external clock) with a duty
of 50%. During slave mode, this pin
inputs the external data transfer clock.
FLM
264
First line
marker
I/O
1
During master mode, pin FLM outputs
the first line marker. During slave mode,
this pin inputs the external data first line
marker. The shift direction of the first
line marker is determined by DUTY and
SHL signal as follows. Set signal DUTY
to high during slave mode. See Table 5.
M
262
M
I/O
1
Pin M inputs and outputs the alternating
signal of the LCD output.


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