Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

CY7C1372DV25-167 Datasheet(PDF) 1 Page - Cypress Semiconductor

Part # CY7C1372DV25-167
Description  18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1372DV25-167 Datasheet(HTML) 1 Page - Cypress Semiconductor

  CY7C1372DV25-167 Datasheet HTML 1Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 2Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 3Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 4Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 5Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 6Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 7Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 8Page - Cypress Semiconductor CY7C1372DV25-167 Datasheet HTML 9Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 1 / 30 page
background image
18-Mbit (512K x 36/1M x 18) Pipelined SRAM
with NoBL™ Architecture
CY7C1370DV25
CY7C1372DV25
PRELIMINARY
Cypress Semiconductor Corporation
3901 North First Street
San Jose
, CA 95134
408-943-2600
Document #: 38-05558 Rev. *A
Revised November 9, 2004
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200, and 167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in lead-free 100 TQFP, 119 BGA, and 165 fBGA
packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370DV25 and CY7C1372DV25 are 2.5V, 512K x
36 and 1 Mbit x 18 Synchronous pipelined burst SRAMs with
No Bus Latency™ (NoBL
) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1370DV25 and
CY7C1372DV25 are equipped with the advanced (NoBL) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of data in systems that
require frequent Write/Read transitions. The CY7C1370DV25
and CY7C1372DV25 are pin-compatible and functionally
equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370DV25 and BWa–BWb for
CY7C1372DV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
A0, A1, A
C
MODE
BWa
BWb
WE
CE1
CE2
CE3
OE
READ LOGIC
DQs
DQPa
DQPb
DQPc
DQPd
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0
Q1
Q0
A0
A1
C
ADV/LD
ADV/LD
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
E
CLK
CEN
WRITE
DRIVERS
BWc
BWd
ZZ
SLEEP
CONTROL
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
Logic Block Diagram-CY7C1370DV25 (512K x 36)


Similar Part No. - CY7C1372DV25-167

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1372DV25-167AXC CYPRESS-CY7C1372DV25-167AXC Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1372DV25-167AXC CYPRESS-CY7C1372DV25-167AXC Datasheet
774Kb / 30P
   18-Mbit (512 K 횞 36/1 M 횞 18) Pipelined SRAM with NoBL??Architecture
CY7C1372DV25-167AXI CYPRESS-CY7C1372DV25-167AXI Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1372DV25-167BGC CYPRESS-CY7C1372DV25-167BGC Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1372DV25-167BGI CYPRESS-CY7C1372DV25-167BGI Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
More results

Similar Description - CY7C1372DV25-167

ManufacturerPart #DatasheetDescription
logo
Cypress Semiconductor
CY7C1370D CYPRESS-CY7C1370D_06 Datasheet
511Kb / 28P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1370DV25 CYPRESS-CY7C1370DV25_06 Datasheet
553Kb / 27P
   18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL??Architecture
CY7C1370D CYPRESS-CY7C1370D Datasheet
344Kb / 30P
   18-Mbit (512K X 36/1M X 18) Pipelined SRAM with NoBL Architecture
CY7C1370CV25 CYPRESS-CY7C1370CV25 Datasheet
712Kb / 27P
   512K x 36/1M x 18 Pipelined SRAM with NoBL??Architecture
CY7C1370C CYPRESS-CY7C1370C Datasheet
704Kb / 27P
   512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1372BV25 CYPRESS-CY7C1372BV25 Datasheet
726Kb / 26P
   512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
CY7C1460AV33 CYPRESS-CY7C1460AV33 Datasheet
395Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV25 CYPRESS-CY7C1460AV25_06 Datasheet
511Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV33 CYPRESS-CY7C1460AV33_06 Datasheet
513Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
CY7C1460AV25 CYPRESS-CY7C1460AV25 Datasheet
396Kb / 27P
   36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL??Architecture
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com