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MK2746GT Datasheet(PDF) 4 Page - Integrated Circuit Systems |
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MK2746GT Datasheet(HTML) 4 Page - Integrated Circuit Systems |
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4 / 5 page  DVD/MPEG CLOCK SOURCE MDS 2746 A 4 Revision 100802 In te gr ated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 ● tel (4 08) 295-9 800 ● www.icst.com MK2746 Recommended Operation Conditions DC Electrical Characteristics VDD=3.3 V ±10% , Ambient temperature 0 to +70°C, unless stated otherwise AC Electrical Characteristics VDD = 3.3 V ±10%, Ambient Temperature 0 to +70° C, unless stated otherwise Note 1: Measured with 15 pF Load. Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 °C Power Supply Voltage (measured in respect to GND) +3.0 +3.6 V Parameter Symbol Conditions Min. Typ. Max. Units Operating Voltage VDD 3.0 3.6 V Input High Voltage VIH input selects 2.0 V Input Low Voltage VIL input selects 0.8 V Input High Voltage VIH ICLK (VDD/2)-1 VDD/2 V Input Low Voltage VIL ICLK VDD/2 (VDD/2)+1 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA 0.4 V Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 V Operating Supply Current IDD No load 40 mA Short Circuit Current IOS ±70 mA Input Capacitance CIN 5pF Nominal Output Impedance ZOUT 20 Ω On Chip Pull-up Resistor RPU AS1, AS0 pins 120 k Ω PS1 pin 510 k Ω Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 27 MHz Output Rise Time tOR 20% to 80% of VDD, Note 1 1.0 1.8 ns Output Fall Time tOF 80% to 20% of VDD, Note 1 1.0 1.8 ns Output Clock Duty Cycle tD at VDD/2, Note 1 40 50 60 % Maximum Output Jitter, short term, peak to peak tJ PCLK output, Note 1 +100 ps Maximum Output Jitter, short term, peak to peak tJ All clocks, except PCLK, Note 1 +200 ps Maximum Output Jitter, long term, peak to peak tJ 1000 cycles, except ACLK, Note 1 750 ps |
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