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LM95235 Datasheet(PDF) 23 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part No. LM95235
Description  Precision Remote Diode Temperature Sensor with SMBus Interface and TruTherm Technology
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM95235 Datasheet(HTML) 23 Page - National Semiconductor (TI)

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3.0 Applications Hints (Continued)
Pentium 4 on 0.13
micron process, 2
- 3.06 GHz
1.0011
1.0021
1.0030
3.64
Pentium 4 on 90
nm process
1.0083
1.011
1.023
3.33
Intel Processor on
65 nm process
1.000
1.009
1.050
4.52
Pentium M
(Centrino)
1.00151
1.00220
1.00289
3.06
MMBT3904
1.003
AMD Athlon MP
model 6
1.002
1.008
1.016
AMD Athlon 64
1.008
1.008
1.096
AMD Opteron
1.008
1.008
1.096
AMD Sempron
1.00261
0.93
3.1.3 Compensating for Different Non-Ideality
In order to compensate for the errors introduced by non-
ideality, the temperature sensor is calibrated for a particular
processor. National Semiconductor temperature sensors are
always calibrated to the typical non-ideality and series resis-
tance of a given processor type. The LM95235 is calibrated
for two non-ideality factors and series resistance values thus
supporting the MMBT3904 transistor and Intel processors on
65nm process without the requirement for additional trims.
For most accurate measurements TruTherm mode should
be turned on when measuring the Intel processor on 65nm
process to minimize the error introduced by the false non-
ideality spread (see Section 3.1.1 Diode Non-Ideality Factor
Effect on Accuracy). When a temperature sensor calibrated
for a particular processor type is used with a different pro-
cessor type, additional errors are introduced.
Temperature errors associated with non-ideality of different
processor types may be reduced in a specific temperature
range of concern through use of software calibration. Typical
Non-ideality specification differences cause a gain variation
of the transfer function, therefore the center of the tempera-
ture range of interest should be the target temperature for
calibration purposes. The following equation can be used to
calculate the temperature correction factor (T
CF) required to
compensate for a target non-ideality differing from that sup-
ported by the LM95235.
(7)
where
η
S = LM95235 non-ideality for accuracy specification
η
PROCESSOR
= Processor thermal diode typical non-
ideality
T
CR = center of the temperature range of interest in ˚C
The correction factor should be directly added to the tem-
perature reading produced by the LM95235. For example
when using the LM95235, with the 3904 mode selected, to
measure a AMD Athlon processor, with a typical non-ideality
of 1.008, for a temperature range of 60 ˚C to 100 ˚C the
correction factor would calculate to:
(8)
Therefore, 1.75˚C should be subtracted from the tempera-
ture readings of the LM95235 to compensate for the differing
typical non-ideality target.
3.2 PCB LAYOUT FOR MINIMIZING NOISE
In a noisy environment, such as a processor mother board,
layout considerations are very critical. Noise induced on
traces running between the remote temperature diode sen-
sor and the LM95235 can cause temperature conversion
errors. Keep in mind that the signal level the LM95235 is
trying to measure is in microvolts. The following guidelines
should be followed:
1.
V
DD should be bypassed with a 0.1 µF capacitor in
parallel with 100 pF. The 100 pF capacitor should be
placed as close as possible to the power supply pin. A
bulk capacitance of approximately 10 µF needs to be in
the near vicinity of the LM95235.
2.
A 100 pF diode bypass capacitor is recommended to
filter high frequency noise but may not be necessary.
Make sure the traces to the 100 pF capacitor are
matched. Place the filter capacitors close to the
LM95235 pins.
3.
Ideally, the LM95235 should be placed within 10 cm of
the Processor diode pins with the traces being as
straight, short and identical as possible. Trace resis-
tance of 1
Ω can cause as much as 0.62˚C of error. This
error can be compensated by using simple software
offset compensation.
4.
Diode traces should be surrounded by a GND guard ring
to either side, above and below if possible. This GND
guard should not be between the D+ and D− lines. In the
event that noise does couple to the diode lines it would
be ideal if it is coupled common mode. That is equally to
the D+ and D− lines.
5.
Avoid routing diode traces in close proximity to power
supply switching or filtering inductors.
6.
Avoid running diode traces close to or parallel to high
speed digital and bus lines. Diode traces should be kept
at least 2 cm apart from the high speed digital traces.
7.
If it is necessary to cross high speed digital traces, the
diode traces and the high speed digital traces should
cross at a 90 degree angle.
8.
The ideal place to connect the LM95235’s GND pin is as
close as possible to the Processors GND associated
with the sense diode.
20174917
FIGURE 8. Ideal Diode Trace Layout
www.national.com
23


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