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LM95235 Datasheet(PDF) 17 Page - National Semiconductor (TI) |
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LM95235 Datasheet(HTML) 17 Page - National Semiconductor (TI) |
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17 / 25 page  2.0 LM95235 Registers (Continued) For data synchronization purposes, the MSB register should be read first if the user wants to read both MSB and LSB registers. The LSB will be locked after the MSB is read. The LSB will be unlocked after being read. If the user reads MSBs consecutively, each time the MSB is read, the LSB associated with that temperature will be locked in and override the previous LSB value locked-in. 2.2 DIODE CONFIGURATION REGISTERS Configuration Register 2 (Read/write Address BFh): D7 D6 D5 D4 D3 D2 D1 D0 0 OS/A0 Function Select OS Fault Mask T_CRIT Mask TruTherm Select RFE1 RFE0 1 Bits Name Description 7 Reserved Reports "0" when read. 6 OS/A0 Function Select 0: Address (A0) function is enabled 1: Over-temperature Shutdown (OS) is enabled 5 Diode Fault Mask for OS 0: Off 1: On 4 Diode Fault Mask for T_CRIT 0: Off 1: On 3 Remote Diode TruTherm Mode Select 0: Selects Diode Model 2, MMBT3904, with TruTherm technology disabled. 1: Selects Diode Model 1, A typical Intel Processor, with 65 nm or 90 nm technology, and TruTherm technology enabled. 2-1 Remote Filter Enable 00: Filter Disable 01: Reserved 10: Reserved 11: Filter Enable 0 Reserved Reports "1" when read. Power up default is 1Fh. Remote Offset High Byte (2’s Complement) (R/W Address 11h) 10-bit plus sign format: BIT D7 D6 D5 D4 D3 D2 D1 D0 Value SIGN 64 32 16 8 4 2 1 Power up default is 00h. Remote Offset Low Byte (2’s Complement) (R/W Address 12h) 10-bit plus sign format: BIT D7 D6 D5 D4 D3 D2 D1 D0 Value 0.50 0.25 0.125 0000 0 Power up default is 00h. LSb = 0.125 ˚C. www.national.com 17 |
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