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IS80LV52-24PQI Datasheet(PDF) 7 Page - Integrated Silicon Solution, Inc |
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IS80LV52-24PQI Datasheet(HTML) 7 Page - Integrated Silicon Solution, Inc |
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7 / 48 page  IS80LV52 IS80LV32 Integrated Silicon Solution, Inc. — 1-800-379-4774 7 ADVANCE INFORMATION MC019-0A 10/01/98 ISSI® OPERATING DESCRIPTION The detail description of the IS80LV52/32 included in this description are: •Memory Map and Registers •Timer/Counters •Serial Interface •Interrupt System •Other Information MEMORY MAP AND REGISTERS Memory The IS80LV52/32 has separate address spaces for program and data memory. The program and data memory can be up to 64K bytes long. The lower 8K program memory can reside on-chip. (IS80LV52 only) Figure 5 shows a map of the IS80LV52/32 program and data memory. The IS80LV52/32 has 256 bytes of on-chip RAM, plus numbers of special function registers. The lower 128 bytes can be accessed either by direct addressing or by indirect addressing. The upper 128 bytes can be accessed by indirect addressing only. Figure 6 shows internal data memory organization and SFR Memory Map. The lower 128 bytes of RAM can be divided into three segments as listed below and shown in Figure 7. 1. Register Banks 0-3: locations 00H through 1FH (32 bytes). The device after reset defaults to register bank 0. To use the other register banks, the user must select them in software. Each register bank contains eight 1-byte registers R0-R7. Reset initializes the stack point to location 07H, and is incremented once to start from 08H, which is the first register of the second register bank. 2. Bit Addressable Area: 16 bytes have been assigned for this segment 20H-2FH. Each one of the 128 bits of this segment can be directly addressed (0-7FH). Each of the 16 bytes in this segment can also be addressed as a byte. 3. Scratch Pad Area: 30H-7FH are available to the user as data RAM. However, if the data pointer has been initialized to this area, enough bytes should be left aside to prevent SP data destruction. FFFFH: 64K 1FFFH: 8K Program Memory (Read Only) Data Memory (Read/Write) EA = 0 External PSEN EA = 1 Internal (IS80C52 Only) 0000 00 FFFFH: External Internal FFH: 0000 RD WR Figure 5. IS80LV52/32 Program and Data Memory Structure |
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