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IR3088MTR Datasheet(PDF) 7 Page - International Rectifier |
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IR3088MTR Datasheet(HTML) 7 Page - International Rectifier |
7 / 34 page IR3088 PWM Control Method The PWM block diagram of the XPhase TM architecture is shown in Figure 2. Feed-forward voltage mode control with trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes in load current. + - 10K SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER X34 X 0.91 20mV + - 10K SHARE ADJUST ERROR AMPLIFIER CURRENT SENSE AMPLIFIER X34 20mV X 0.91 + - DACIN PWMRMP BIASIN RAMPIN- RAMPIN+ GATEH SCOMP ISHARE CSIN+ GATEL EAIN CSIN- SYSTEM REFERENCE VOLTAGE ENABLE CLOCK PULSE GENERATOR BODY BRAKING COMPARATOR RAMP DISCHARGE CLAMP PWM LATCH S RESET DOMINANT PHASE IC R PWM COMPARATOR RDRP RPWMRMP RPHS2 CSCOMP RPHS1 RCS RVFB CPWMRMP CSCOMP CCS RPWMRMP RCS + - CPWMRMP CCS RPHS2 RPHS1 + - GND VOUT BIASIN VDAC VBIAS DACIN PWMRMP RAMPIN+ VOSNS- VOSNS+ VOSNS- ISHARE RAMPIN- IIN VDRP EAIN GATEH SCOMP CSIN- CSIN+ GATEL EAOUT RMPOUT VIN FB IROSC SYSTEM REFERENCE VOLTAGE VDAC BODY BRAKING COMPARATOR RAMP DISCHARGE CLAMP ENABLE CLOCK PULSE GENERATOR VBIAS REGULATOR IFB VDRP AMP 50% DUTY CYCLE RAMP GENERATOR VVALLEY VPEAK ERROR AMP R S RESET DOMINANT PWM LATCH PHASE IC COUT CONTROL IC PWM COMPARATOR Figure 2. PWM Block Diagram Frequency and Phase Timing Control An oscillator with programmable frequency is located in the Control IC. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of approximately 5V and 1V respectively. This signal is used to program both the switching frequency and phase timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for phase timing by swapping the RMPIN+ and RMPIN– pins, as shown in Figure 2. Page 7 of 34 9/30/04 |
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