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LC72315W Datasheet(PDF) 9 Page - Sanyo Semicon Device |
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LC72315W Datasheet(HTML) 9 Page - Sanyo Semicon Device |
9 / 12 page No. 6650-9/12 LC72314W, 72315W, 72316W Continued from preceding page. Pin No. Pin I/O Function I/O circuit System reset input. In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. 72 RES I Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception mode. 38 VDC1 O Voltage stepped up by the DC-DC converter (3 V) May also be used to input an equivalent voltage. 37 VDC3 I RAM backup power supply. Connected to the VDC3 voltage through a diode. 36 VDDRAM I VDC3 voltage adjustment pin. Insert a 10 k Ω variable resistor between this pin and ground to adjust the VDC3 voltage. 39 VADJ O FM VCO (local oscillator) input. This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. 75 FMIN I CMOS amplifier input AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. 76 AMIN I CMOS amplifier input Dedicated input port for the universal counter. • For frequency measurement, select the HCTR frequency measurement mode and measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the counter with a UCC instruction. When the count operation completes, the CNTEND flag will be set. Since it operates as an AC amplifier in this mode, the input must be provided through a coupling capacitor. Input is disabled in backup mode, HALT mode, after a reset, and in PLL STOP mode. 73 HCTR I CMOS amplifier input Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output, and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 78 EO O Power supply pin. This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. Supports A/D converter. — 77 35 74 VSS VSS VDD — CMOS push-pull CW1 b1, b0 Input pins Bandwidth 1 0 AMIN (H) 2 to 20 MHz (SW) 1 1 FMIN (L) 0.5 to 10 MHz (MW, LW) UCS b3, b2 Input pin measurement mode 0 0 HCTR frequency measurement 0 1 — 1 1 — UCS b1, b0 Measurement time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 32 ms Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction. |
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