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CDC930 Datasheet(PDF) 1 Page - Texas Instruments

Part No. CDC930
Description  133-MHz DIFFERENTIAL CLOCK SYNTHESIZER / DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDC930 Datasheet(HTML) 1 Page - Texas Instruments

 
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SCAS641
– JULY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Generates Clocks for Pentium 4
Microprocessors
Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
Theoretical EMI Damping of 7 dB
Power Management Control Terminals
Low Output Skew and Jitter for Clock
Distribution
Operates From Single 3.3-V Supply
Consumes Less Than 30-mA Power-Down
Current
Generates the Following Clocks:
– 4 HCLK (Host) (Different Pairs–
100/133 MHz)
– 1 3VMREF Pair (3.3 V, 180 Shifted
50/66 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 4 3V66 MHz (3.3 V, 66 MHz)
– 2 3V48 MHz (3.3 V, 48 MHz)
Packaged in 56-Pin SSOP Package
description
The CDC930 is a differential clock synthesizer/
driver that generates HCLK/HCLK, 3VMREF/
3VMREF, PCI, 3V66, 3V48, REF system clock
signals to support a computer system with a
Pentium 4
microprocessor
and
a
Direct
Rambus
memory subsystem.
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external
components. The host, PCI clock and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable
clock operation. All outputs have 3-state capability, which can be selected using control inputs SEL133, SelA
and SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down
mode in which HCLK is driven at 2 IREF, HCLK is not driven, and all others are set low.
Copyright
2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†This is system design dependant.
Intel and Pentium 4 are trademarks of Intel Corporation.
Rambus is a trademark of Rambus Corporation.
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GND
REF0/MultSel0
REF1/MultSel1
VDD3.3V
XIN
XOUT
GND
PCI0
PCI1
VDD3.3V
PCI2
PCI3
GND
PCI4
PCI5
VDD3.3V
PCI6
PCI7
GND
PCI8
PCI9
VDD3.3V
SEL100/133
GND
3V48(0)/SelA
3V48(1)/SelB
VDD3.3V
PWRDWN
VDD3.3V
3VMREF
3VMREF
GND
SPREAD
HCLK(1)
HCLK(1)
VDD3.3V
HCLK(2)
HCLK(2)
GND
HCLK(3)
HCLK(3)
VDD3.3V
HCLK(4)
HCLK(4)
GND
I_REF
VDD3.3V
GND
VDD3.3V
3V66(0)
3V66(1)
GND
GND
3V66(2)
3V66(3)
VDD3.3V
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