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ARM940T Datasheet(PDF) 81 Page - List of Unclassifed Manufacturers |
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ARM940T Datasheet(HTML) 81 Page - List of Unclassifed Manufacturers |
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81 / 230 page  Bus Interface Unit ARM DDI 0144B Copyright © 1999, 2000 ARM Limited. All rights reserved. 6-5 The following timing diagrams show the types of transfer that can be initiated by the ARM940T rev1: • Example LDR from address 0x108 on page 6-6 • Example LDM of 5 words from 0x108 on page 6-7 • Example nonbuffered STR on page 6-9 • Example STM on page 6-10 • Example linefill from 0x100 on page 6-12 • Cache linefill and write back on page 6-13 • Example 4-word data eviction on page 6-14 • Example swap operation on page 6-15. The AREQ and AGNT signals and the responses from the ASB slave are not shown in these diagrams. It is assumed that AGNT is asserted and the ASB slave response is DONE. Different slave responses and bus master handover are covered in the AMBA Specification (Rev 2.0). It is assumed that you are using the ARM940T macrocell within a multi-master ASB system, so unidirectional ASB timing diagrams are not provided. 6.2.1 Noncached LDRs and noncached fetches The only difference between these noncached LDRs and noncached fetches is the BPROT[1:0] information, as shown in Table 6-3 on page 6-5. The address is word-aligned for an LDR and fetch. An example LDR is shown in Figure 6-1 on page 6-6. Table 6-3 Noncached LDR and fetch BPROT[0] Transfer 0 Opcode fetch 1 Data access |
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