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ARM940T Datasheet(PDF) 65 Page - List of Unclassifed Manufacturers |
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ARM940T Datasheet(HTML) 65 Page - List of Unclassifed Manufacturers |
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65 / 230 page  Caches and Write Buffer ARM DDI 0144B Copyright © 1999, 2000 ARM Limited. All rights reserved. 4-17 Data cache lockdown For the DCache, the procedure is as follows: 1. Write to CP15 register 9, setting DL=1 and Dindex=0. 2. Initialize the pointer to the first of the 16 words to be locked. 3. Execute an LDR from that location. This forces a linefill from that location, and the resulting four words are captured by the cache. 4. Increment the pointer by 16 to select cache segment 1. 5. Execute an LDR from that location. The resulting linefill is captured in cache segment 2. 6. Repeat steps 1 to 5 for cache segments 3 and 4. 7. Write to CP15 register 9, setting DL=0 and Dindex=1. If there is more data to lockdown, at the final step, step 7, the DL bit must be left HIGH, Dindex incremented by 1 line, and the process repeated. The DL bit must only be set LOW when all the lockdown data has been loaded. Instruction cache lockdown For the ICache, this procedure is as follows: 1. Write to CP15 register 9, setting IL=1 and Iindex=0. 2. Initialize the pointer to the first of the sixteen words to lockdown. 3. Force a linefill from that location by writing to CP15 register 7. 4. Increment the pointer by 16 to select cache segment 1. 5. Force a linefill from that location by writing to CP15 register 7. The resulting linefill is captured in segment 1. 6. Repeat for cache segments 3 and 4. 7. Write to CP15 register 9, setting IL=0 and Iindex=1. If there is more data to lockdown, at the final step 7, the IL bit must be left HIGH, Iindex incremented by 1 line, and the process repeated. The IL bit must be set LOW when all the lockdown data has been loaded. |
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