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ICS951402YGLF-T Datasheet(PDF) 9 Page - Integrated Circuit Systems |
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ICS951402YGLF-T Datasheet(HTML) 9 Page - Integrated Circuit Systems |
9 / 23 page 9 Integrated Circuit Systems, Inc. ICS951402 Advance Information 0660—05/05/05 I 2C Table: Watchdog Timer Register Byte 9 Pin # Name Control Function Type 0 1 PWD Bit 7 - WD7 RW - - 0 Bit 6 - WD6 RW - - 0 Bit 5 - WD5 RW - - 0 Bit 4 - WD4 RW - - 1 Bit 3 - WD3 RW - - 0 Bit 2 - WD2 RW - - 0 Bit 1 - WD1 RW - - 0 Bit 0 - WD0 These bits represent X*293ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 293ms =4.688 seconds RW - - 0 I 2C Table: WD Timer Control Register Byte 10 Pin # Name Control Function Type 0 1 PWD Bit 7 - M/NEN M/N Programming Enable RW Latched Inputs IIC Prog. B (11:17) 0 Bit 6 - WDEN Watchdog Enable RW Disable Enable 0 Bit 5 - WDStatus WD Status Control RW OFF ON 0 Bit 4 - WD SF4 RW - - 1 Bit 3 - WD SF3 RW - - 0 Bit 2 - WD SF2 RW - - 0 Bit 1 - WD SF1 RW - - 0 Bit 0 - WD SF0 Writing to these bit will configure the safe frequency as Byte 0 Bit (6:0 ) RW - - 0 Note: If Byte4 bit1 = 0 then FS4=0 I 2C Table: VCO Frequency Control Register Byte 11 Pin # Name Control Function Type 0 1 PWD Bit 7 - N Div8 N Divider Bit 8 RW - - X Bit 6 - M Div6 RW - - X Bit 5 - M Div5 RW - - X Bit 4 - M Div4 RW - - X Bit 3 - M Div3 RW - - X Bit 2 - M Div2 RW - - X Bit 1 - M Div1 RW - - X Bit 0 - M Div0 The decimal representation of M Div (6:0) is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. RW - - X |
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