8 / 36 page
CY7C68300B/CY7C68301B
CY7C68320/CY7C68321
Document 38-08033 Rev. *D
Page 8 of 36
N/A
N/A
28
NC
No Connect.
22
15
29
SCL
O
Active for
several ms at
start-up.
Clock signal for I2C interface (see section 5.3.2).
23
16
30
SDA
I/O
Data signal for I2C interface (see section 5.3.2).
N/A
N/A
31
32
NC
No Connect.
24
17
33
VCC
PWR
VCC. Connect to 3.3V power source.
25
18
34
DD0
I/O[1]
Hi-Z
ATA Data bit 0.
26
19
35
DD1
I/O[1]
Hi-Z
ATA Data bit 1.
27
20
36
DD2
I/O[1]
Hi-Z
ATA Data bit 2.
28
21
37
DD3
I/O[1]
Hi-Z
ATA Data bit 3.
N/A
N/A
38
VCC
PWR
VCC. Connect to 3.3V power source.
N/A
N/A
39
GND
GND
Ground.
N/A
N/A
40
NC
NC
No Connect.
N/A
N/A
41
GND
Ground.
N/A
N/A
42
NC
NC
No Connect.
N/A
N/A
43
GND
Ground.
29
22
44
DD4
I/O[1]
Hi-Z
ATA Data bit 4.
30
23
45
DD5
I/O[1]
Hi-Z
ATA Data bit 5.
31
24
46
DD6
I/O[1]
Hi-Z
ATA Data bit 6.
32
25
47
DD7
I/O[1]
Hi-Z
ATA Data bit 7.
33
26
48
GND
GND
Ground.
34
27
49
VCC
PWR
VCC. Connect to 3.3V power source.
35
28
50
GND
GND
Ground.
N/A
N/A
51
52
NC
NC
No Connect.
N/A
N/A
53
VCC
PWR
VCC. Connect to 3.3V power source.
36
29
54
DIOW#[2]
O/Z[1]
Driven HIGH
(CMOS)
ATA Control.
37
30
55
DIOR#
O/Z[1]
Driven HIGH
(CMOS)
ATA Control.
38
31
56
DMACK#
O/Z[1]
Driven HIGH
(CMOS)
ATA Control.
N/A
N/A
57
NC
NC
No Connect.
N/A
N/A
58
LOWPWR#
O
USB suspend indicator (see section 5.3.7).
‘0’ = Chip active. VBUS power draw governed by
PWR500# pin.
‘Hi-Z’ = Chip suspend. VBUS system current limited to
USB suspend mode value.
N/A
N/A
59
60
61
NC
NC
No Connect.
N/A
N/A
62
VBUSPWRD
I
Input
Bus-powered operation selector. Used in systems
that are capable of being bus or self-powered to
indicate the current power mode.
N/A
N/A
63
64
NC
NC
No Connect.
N/A
N/A
65
GND
GND
Ground.
Table 5-1. AT2LP Pin Descriptions
Note: (Italics pin names denote pin functionality during CY7C68300A-compatibility mode) (continued)
56
SSOP
56
QFN
100
TQFP
Pin Name
Pin
Type
Default State
at Start-up
Pin Description
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