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W65C51S Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers

Part No. W65C51S
Description  Asynchronous Communications Interface Adapter (ACIA)
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Maker  ETC1 [List of Unclassifed Manufacturers]
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W65C51S Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers

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6
CONTROL REGISTER
The Control Register selects the desired baud rate, frequency
source, word length and the number of stop bits.
7
6
5
4
3
2
1
0
WL
SBR
SBN
WL1
WL0
RCS
SBR3
SBR2
SBR1
SBR0
Bit 7
Stop Bit Number (SBN)
0
1 Stop bit
1
2 Stop bits
1
1 ½ Stop bits
For WL = 5 and no parity
1
1 Stop bit
For WL = 8 and parity
Bits 6-5
Word Length (WL)
6
5
No. Bits
0
0
8
0
1
7
1
0
6
1
1
5
Bit 4
Receiver Clock Source (RCS)
0
External receiver clock
1
Baud rate
Bit 3-0
Selected Baud Rate (SBR)
3
2
1
0
Baud
0
0
0
0
16x
0
0
0
1
50
0
0
1
0
75
0
0
1
1
109.92
0
1
0
0
134.58
0
1
0
1
150
0
1
1
0
300
0
1
1
1
600
1
0
0
0
1200
1
0
0
1
1800
1
0
1
0
2400
1
0
1
1
3600
1
1
0
0
4800
1
1
0
1
7200
1
1
1
0
9600
1
1
1
1
19,200
Reset Initialization
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Hardware reset (RESB)
-
-
-
-
-
-
-
-
Program reset
Selected Baud Rate (Bits 0, 1, 2, 3)
These bits select the Transmitter baud rate, which can be at
1/16 an external clock rate or one of 15 other rates controlled
by the internal baud rate generator.
If the Receiver clock uses the same baud rate at the
transmitter, then RxC becomes an output and can be used to
slave other circuits to the ACIA.
Figure 3 shows the
Transmitter and Receiver layout.
RECEIVER
SHIFT REGISTER
CLOCK
DIVIDER
(16)
CONTROL
REGISTER
BIT 4
BAUD RATE
GENERATOR
CLOCK
DIVIDER
(16)
BITS 0-3 IN
CONTROL
REGISTER
TRANSMITTER
SHIFT REGISTER
SYNC
LOGIC
XTLI
XTLO
TxD
RxC
RxD
Figure 4 Transmitter/Receiver Clock Circuits
Receiver Clock Source (Bit 4)
This bit controls the clock source to the Receiver. A 0 causes
the Receiver to operate at a baud rate of 1/16 an external
clock. A 1 causes the Receiver to operate at the same baud
rate as is selected for the transmitter.
Word Length (Bits 5, 6)
These bits determine the word length to be used (5, 6, 7 or 8
bits).
Stop Bit Number (Bit 7)
This bit determines the number of stop bits used. A 0 always
indicates one stop bit. A 1 indicates 1½ stop bits if the word
length is 5 with no parity selected, 1 stop bit if the word
length is 8 with parity selected and 2 stop bits in all other
configurations.


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