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W65C51S Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. W65C51S
Description  Asynchronous Communications Interface Adapter (ACIA)
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Maker  ETC1 [List of Unclassifed Manufacturers]
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W65C51S Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

 
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5
STATUS REGISTER
The Status Register indicates the state of interrupt conditions
and other non-interrupt status lines. The interrupt conditions
are the Data Set Ready, Data Carrier Detect, Transmitter
Data Register Empty and Receiver Data Register Full as
reported in bits 6 through 3, respectively. If any of these bits
are set the interrupt (IRQ) indicator (bit 7) is also set.
Overrun, Framing Error and Parity Error are also reported
(bits 2 through 0 respectively).
Bit 7
Interrupt (IRQ)
0
No Interrupt
1
Interrupt has occurred
Bit 6
Data Set Ready (DSRB)
0
DSR low (ready)
1
DSR high (not ready)
Bit 5
Data Carrier Detect (DCDB)
0
DCD low (detected)
1
DCD high (not detected)
Bit 4
Transmitter Data Register Empty
0
Not Empty
1
Empty
Bit 3
Receiver Data Register Full
0
Not full
1
Full
Bit 2
Overrun*
0
No overrun
1
Overrun has occurred
Bit 1
Framing Error*
0
No framing error
1
Framing error detected
Bit 0
Parity Error*
0
No parity error
1
Parity error detected
*No interrupt occurrs for these conditions
Reset Initialization
7
6
5
4
3
2
1
0
0
-
-
1
0
0
0
0
Hardware reset
-
-
-
-
-
0
-
-
Program reset
Parity error (Bit 0) Framing Error (Bit 1) and Overrun
(Bit 2)
None of these bits causes a processor interrupt to occur but,
they are normally checked at the time the Receiver Data
Register is read so that the validity of the data can be
verified.
These bits are self clearing (i.e., they are
automatically cleared after a read of the Receiver Data
Register).
Receiver Data Register Full (Bit 3)
This bit goes to a 1 when the ACIA transfers data from the
Receiver Shift Register to the Receiver Data Register and
goes to a 0 (is cleared) when the processor reads the Receiver
Data Register.
Transmitter Data Register Empty (Bit 4)
This bit goes to a 1 when the ACIA transfers data from the
Transmitter Data Register to the Transmitter Shift Register
and goes to a 0 (is cleared) when the processor writes new
data onto the Transmitter Data Register.
Data Carrier Detect (Bit 5) and Data Set Ready (Bit 6)
These bits reflect the levels of the DCDB and DSRB inputs
to the ACIA. A 0 indicates a low level (true condition) and a
1 indicates a high level (false). Whenever either of these
inputs change state, an immediate processor interrupt (IRQ)
occurs, unless bit 1 of the Command Register (IRD) is set to
a 1 to disable IRQB. When the interrupt occurs, the status
bits indicate the levels of the inputs immediately after the
change of state occurred. Subsequent level changes will not
affect the status bits until the Status Register is interrogated
by the processor.
At that time, another interrupt will
immediately occur and the status bits reflect the new input
levels. These bits are not automatically cleared (or reset) by
an internal operation.
Interrupt (Bit 7)
This bit goes to a 1 whenever an interrupt condition occurs
and goes to a 0 (is cleared) when the Status Register is read.
7
6
5
4
3
2
1
0
IRQ
DSRB
DCDB
TDRE
RDRF
OVRN
FE
PE


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